Search Results for "exe-generator"
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Showing 2 open source projects for "exe-generator"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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LavaRnd is a random number generator that converts a digitized chaotic source (such as a lens capped web camera) into cryptographically strong random numbers. LavaRnd comes with both an APIs (currently C and Perl) as well as a number of demos.
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