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This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
The goal of the c6x-tools project is to provide an Open Source
development environment for users of the TI TMS320C6x DSP family. This includes (but is not limited to) the following commonly-used devices: 'C6211, 'C6711, 'C6201 and 'C6701.
The GDB (GNU debugger) RSP (remote serial protocol) allows remote debugging of embedded software. This project offers sourcecode of monitors so the developer only needs to burn flash EPROMs once, then use serial communication to download/debug.