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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23.
Project Fish is a start kit for those who want to have study with ARM/PCB/DDK/.Net. PF will start from a Digital thermometer, with the implement of Hard ware design, firmware, Windows driver and app, the participator will got understading in that fields.
Voxampp is an Enterprise IP TriplePlay Application Stack (eIPTAS) a - run-time toolkit - for Internet Entrepreneurs that want to deploy rich IP Carrier Networks. Its goal, to facilitate worldwide Open Access Social Networks using IPTV, VoIP and much more