Search Results for "clock"
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2 projects for "clock" with 2 filters applied:
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MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Dual BCD to Hex 7-Seg Driver
A BCD to Hex Dual 7-Segment Display Driver IC using a PLD
This is the JEDEC and Source for both a Dual 7-Segment Hexadecimal and a Single 7-Segment Hexadecimal Display Driver using GAL22V10 and GAL16V8 PLDs. The driver uses a clocked input to multiplex the displays, so that one display is lit when the clock is high, and the other when the clock is low. With a fast enough clock speed the two displays both appear to be displayed at the same time. The code is written for WinCUPL. See the Instructables page for more details. http://www.instructables.com/id/Dual-BCD-to-Hex-7-Segment-Driver/
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