Search Results for "design"

QMK (Quantum Mechanical Keyboard) is an open source community centered around developing computer input devices. The community encompasses all sorts of input devices, such as keyboards, mice, and MIDI devices. This is a keyboard firmware based on the tmk_keyboard firmware with some useful features for Atmel AVR and ARM controllers, and more specifically, the OLKB product line, the ErgoDox EZ keyboard, and the Clueboard product line. Keyboards powered by QMK are Planck, Preonic, ErgoDox EZ,...

A very high quality package of printer drivers for CUPS on Linux and other POSIX-compliant operating systems. This project also maintains an enhanced Print plug-in for GIMP 2.x from the same code base.

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.

myFocuserPro is an ASCOM and Moonlite compatible stepper motor telescope focus controller (DIY) based on Arduino Nano/Uno. A popular DIY ASCOM focuser with more than 121,000+ downloads. (c) Copyright Robert Brown 2014-2024. All Rights reserved. Permission is granted for personal and Academic use only. Spreadsheet to calculate what stepper motor to use. https://sourceforge.net/projects/arduinoascomfocuserpro2diy/files/Documentation/Nema-Stepper-Motors.xlsx/download

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.

CUPS back-end for the canon printers using the proprietary USB over IP BJNP protocol. This back-end allows Cups to print over the network to a Canon printer. The design is based on reverse engineering of the protocol. Version 2.0 adds ink-level reporting and improved out-of-paper detection. Version 2.0.1 is now released under GPLv2 or later to be compatible with the changed cups license. No other changes. Version 2.0.2 fixes a compile error with GCC9 Version 2.0.3 Fix GCC10 compile errors. increase status buffer size for newer printers that send larger status messages

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

This is a small library that allows comunicating with a Webasto (tm) W-Bus capable car heating system. Runs on Personal Computers or for embedded devices (slim design). Easily portable. Includes a Heater manager, heater controller program and more. The GIT repository (CVS is deprecated) also includes a control unit application to control W-Bus capable devices, a W-Bus compatible heater unit firmware application and a heater simulator for testing purposes. Also, a serial port loop back driver for linux is included to simulate OBD II K-Line adapters.

JNode is a Java New Operating system Design Effort. JNode is a simple to use and install Java operating system for personal use on modern devices. Any java application runs on it, fast and safe. See our homepage for additional information.

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the...

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).

TxEngine is an embedded controller engine designed to allow one to make supervision & control program that fit in embedded systems. Include a modular design with native support for Modbus RTU, timers, threads, linked lists

Software and Arduino shield design for a Serial-to-HID device such that old serial gaming devices can be used as USB Hid devices, particularly the SpaceOrb360 and Spaceball 3d CAD devices.

...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

The goal of the See&Touch project is to design/implement a special mouse for disabled people, which allows a person to fully control a computer by using just vision and one single body movement. This project develops hardware, firmware and software.

The OCCN project enhances SystemC2.0+ modeling by developing C++ classes for modeling user-defined or system-specific, point-to-point or multiaccess inter-module communication channels (or future network-on-chip) at various abstraction levels. To reference this work: M. Coppola, S. Curaba, M.D. Grammatikakis, R. Locatelli, G. Maruccia, and F. Papariello, "OCCN: a NoC modeling framework for design exploration", Design Automation in Europe Conf. (DATE), 2004, pp. 174--179. Available from Available from http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.138.1281&rep=rep1&type=pdf

The primary aim of this project is to develop a full featured Microblaze simulator . The project is develloped only in C , then it can be easely ported.

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

The objectives of OCERA is the design and implementation of a library of free software components for the design of embedded real-time systems. These components will be used to create flexible, configurable, robust and portable embedded applications.

A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

The goal of zAutomation project is to design/implement hardware, firmware and software for remote control and monitoring of physical objects, by using the ZigBee technology and internet. The field of application is robotics and domotics.

BDR (Beowulf Design Rules) is a vendor-neutral software tool that quickly evaluates millions of alternative architectures to determine the best cluster hardware design for your application requirements and budget (e.g., money, space, power consumption).

Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.