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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...
An open hardware and software platform, Octobits attempts to recreate the aesthetics of the early eight-bit computer age using cheap, powerful, and readily available modern components.
SECU86 is Standard Engine Control Unit x86. The project goal is to develop a standard computer and OS (opensource) that would work on any car. It'll be based on the x86 processor and will try to replace the poor standard ECU that comes with any car.