Search Results for "text processing"
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Showing 2 open source projects for "text processing"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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An ethernet sniffer for BrainNet36®
An ethernet sniffer for the EEG acquisition system BrainNet36®
...BrainNet36® has 36 channels, A/D converters with 16 bit accuracy, conversion time of 10 µs and Ethernet communication interface. Being a device for clinical purposes, BrainNet36® does not export data online. This sniffer was developed to allow online processing by working in promiscuous mode and recording data in a plain text file.
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