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SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
Testcard is a SDL/SDL_gfx based monitor test pattern (test card) generator. SMPTE and other test patterns are supported. Future plans include a very basic scripting capability to construct custom test patterns from built in primitives.