Showing 8 open source projects for "binary code generator"

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  • 1
    Open Source Cartridge Reader

    Open Source Cartridge Reader

    A shield for the Arduino Mega that can back up video game cartridges

    ...Supported cartridge types so far, LoRom, HiRom, ExHiRom, DSP, SuperFX, SuperFX2, SDD1, CX4, SPC7110, SA1 (last two chips need Adafruit Clock Generator). Reads and writes SNES Satellaview 8M Memory packs (BS-X cartridge and Adafruit Clock Generator needed). Reads and writes Nintendo Power Super Famicom Memory Flash Cartridges (needs Adafruit Clock Generator for best result).
    Downloads: 1 This Week
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  • 2
    QuickMAN is a Mandelbrot fractal generator with multicore support. ASM-optimized code can reach over 100 billion iterations per second. Features an easy-to-use GUI, realtime pan/zoom, multiple palettes, image logging, and saving in PNG format.
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    Downloads: 10 This Week
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  • 3

    RecordEditor

    Editor for Fixed Width, Csv and Existing Xml files.

    ...It can generally find both Text and binary / packed deicimal fields in a file For Simple Csv you should look at its sister project reCsvEditor. Note: The core Editor code is also used in the "Protocol buffers editor" and "Avro Editor"
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    Downloads: 39 This Week
    Last Update:
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  • 4

    COBOL copybook to XML converter

    Converts cobol copybooks to Xml/Java objects

    CB2XML (CopyBook to XML) is a COBOL CopyBook to XML converter written in Java and based on the SableCC parser generator. This project includes utilities to convert an XML instance file into its COBOL copybook equivalent string buffer and vice versa. Source is now available in GitHub: https://github.com/bmTas/cb2xml
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    Downloads: 22 This Week
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  • 5

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
    Last Update:
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  • 6

    Dual BCD to Hex 7-Seg Driver

    A BCD to Hex Dual 7-Segment Display Driver IC using a PLD

    This is the JEDEC and Source for both a Dual 7-Segment Hexadecimal and a Single 7-Segment Hexadecimal Display Driver using GAL22V10 and GAL16V8 PLDs. The driver uses a clocked input to multiplex the displays, so that one display is lit when the clock is high, and the other when the clock is low. With a fast enough clock speed the two displays both appear to be displayed at the same time. The code is written for WinCUPL. See the Instructables page for more...
    Downloads: 1 This Week
    Last Update:
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  • 7
    CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms
    Downloads: 10 This Week
    Last Update:
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  • 8
    mDriver is a utility to migrate binary device driver from Windows to Linux. It takes out the binary instruction and data from Windows driver (*.sys files), and then combine them with some supporting code to build a corresponding Linux driver module.
    Downloads: 0 This Week
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