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The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
This project is about the graphical simulation of pipelining mechanism in Central Processor Unit. It includes (1) INES Components package created in Delphi, which allows fast building of simple simulators; (2) INES - simulator created with this package.
A hardware description language and simulation tool to describe hardwares based on logic gates. The hardwares described can have the facility to connect to other programs or the devices can be written in C using the program as a library.
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A cycle-accurate interconnection network simulator.
A cycle-accurate interconnection network simulator. Brought to you by the Concurrent VLSI Architecture group at Stanford University. The SourceForge website is no longer actively maintained. Instead, please follow the link in the profile.