Search Results for "java-orm" - Page 2
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Showing 108 open source projects for "java-orm"
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Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
...So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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JReliability allows to derive several reliability-related measures like Mean-Time-To-Failure (MTTF) or Mission-Time (MT) of complex systems that are modeled using Boolean functions, efficiently encoded in Binary Decision Diagrams (BDDs).
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NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.
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Pipes is a desktop system which analyzes an AutoCad(TM) drawing of a sprinkler system, checks for flaws and after these are eliminated, adds the size/diameter labels to the drawing. Tutorial: http://users.norwoodlight.com/janh/wink/autopipes-entry.htm
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...The user builds his system model by selecting predefined blocks from a block library and simply wiring the blocks together. Each block of the diagram performs a function. Users can also create custom blocks in Java and add them to the JMCAD block library. JMCAD is a block diagram language for creating complex nonlinear dynamic systems.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
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TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.
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One Monitoring Tool for IT, OT and Cloud | Free TrialModern infrastructure spans data centers, cloud platforms and factory floors, and every blind spot between them is a risk. PRTG supports SNMP, WMI, SSH and other standard protocols to monitor IT, OT and hybrid environments through one customizable dashboard. Build the views your team needs, from network health to application performance, without switching tools. Try PRTG free for 30 days now.
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Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
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FIBEXplorer
FIBEX format viewer and navigator
Das Field Bus Exchange Format (FIBEX) ist ein XML-Austauschformat für diverse Bussysteme in vernetzten Fahrzeugen. Der Inhalt praxisrelevanter FIBEX-Dateien ist ohne entsprechende Toolunterstützung nur schwer zu fassen. Der FIBEXplorer® bietet einen vielseitigen Viewer für das FIBEX-Format. 100% FIBEX FIBEX Vergleich Linkverfolgung Working Sets Vertikale Navigation Clustered Navigation Startup Wizard By courtesy of Sulzer GmbH (http://www.sulzer.de) -
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Virtual instrumentation software, currently designed for modifying automobile engines. Intended as a modular framework to communicate with devices on an IO port (serial, parallel etc.) and allow a visual representation of the instrument.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
...We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool. -
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Java Decision Diagram Libraries (BDD)
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project has been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home It includes two libraries for working with decision diagrams: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD -
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EEToolbelt
A suite of calculators and conversion tools for engineers.
Includes a signal scaling app, many engineering unit conversion calcs, and a task list pad to keep track of progress or notes. -
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CsvToFootprint
Convert CSV to Kicad footprint.
For electronics engineers, when using open source EDA tools, one of big challenge is component schematic symbols and footprints. If you are creating footprints for component with more than 100 pins, it becomes very time consuming and challenging to create error free footprints. Here is a simple program to create footprints for open source EDA kicad. The idea is to describe footprint in .csv format and convert .csv to kicad footprint format. At preset program supports Kicad only, but can be... -
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Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
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Remote Control for Embedded Device Provide an user interface for a embedded device on a PC or a mobile phone. Communication through RS232, USB, TCP_IP, Bluetooth...
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Power consumption analysis tools for embedded systems. MARTE to AADL model transformation with ATL for tools interoperability. More info on the project at http://sourceforge.net/apps/trac/lab-sticc/
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This program provides for easy modification and viewing of SPICE circuit files. It will also read SPICE3 RAW format (as well as GnuCap) and create graphs of results through an interactive GUI. It supports waveform math, copying to clipboard, and saving.
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Nocmaker is a tool for the design space exploration tool to help in the design of Network on chips. Noc Maker is based on JHDL.
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IPC 175x Utilities is a collection of software tools to support the IPC 1750 series of supplier declaration standards. These utilities are being developed to help electronics industry supply chain stakeholders implement the IPC 1750 series of standard.
