Search Results for "raylib-5.x"
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Showing 21 open source projects for "raylib-5.x"
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Atera all-in-one platform IT management software with AI agentsAtera’s AI agents don’t just assist, they act. From detection to resolution, they handle incidents and requests instantly, taking your IT management from automated to autonomous.
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Free and Open Source HR SoftwareGive your HR team the tools they need to streamline administrative tasks, support employees, and make informed decisions with the OrangeHRM free and open source HR software.
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
...Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database with advance queries 8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning 8.a. ... -
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GLogic
A logic gate simulator for linux developed with Gtk and python.
GLogic is a logic gate simulator for linux and an adaptation of the gLogic package.... -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste... -
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Polonious is an ISO27001 certified secure, extremely flexible and highly configurable investigation workflow solution.The system includes features such as process centrism, workload management, reporting, dynamic dashboards, case reports, integrations and more. With our process and compliance focus, you can ensure your investigations are fully compliant with applicable regulations, with minimal extra effort or stress.
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CAPLET
GDS visualization and parallelized capacitance extraction
Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material. -
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The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.
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Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.
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Raima Database Manager is an embedded in-memory database for IoT and Edge devicesRaima Database Manager (RDM) is an embedded relational database optimized to run on resource-constrained IoT edge devices that require real-time response. RDM enables intelligent decisions to be made at the device level within microseconds.
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ReliaFree is a Python and PyGTK based suite of tools to assist in Reliability, Availability, Maintainability, and Safety (RAMS) analyses. ReliaFree is intended to be an Open Source alternative to proprietary RAMS analyses solutions.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
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Banyan is an enterprise class, web based, information management system that helps people work collaboratively to solve complex problems. Banyan increases project performance and reduces risk through the power of collaborative clear thinking.
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Extensions to the circuit simulator Ngspice. One extension is the integration of the next generation build system SCons.
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The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
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FXPyTurns-n-Layers is a graphical transformer and induction coil design aid. The application performs the physical design of the coils for transformer and induction coils to determine: the length/weight of wire required to wind a coil with the specified
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SVATS [Safety Verification Analysis added To Spice] is a Pyhton written EDA tool used for adding repetitive analysis capabilities to perform FMEAs on analog and mixed analog-digital electronic circuits using Berkeley Spice-like simulation SW
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Blitzer is a simple tool for driving the SX-Blitz microcontroller programmer from Parallax. There is now a version for PalmOS devices.
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