Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
...Maintains a connectivity database with advance queries
8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning
8.a. Insert new hierarchy
8.b. Remove existing hierarchy
9. Associate the IP-XACT memory maps with the SoC component instances
10. Dump out the C Model for the entire design
11. Glue-Logic insertion
12. Spare port insertion across hierarchies
13.
This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).