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Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
...A variety of SoC integration Methodologies
6.a. XLS/CSV Based connections
6.b. Port-to-Port Adhoc connections
6.c. IP-XACT and System Verilog Interface based connections
6.d. ...
7. Maintains a connectivity database with advance queries
8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning
8.a. Insert new hierarchy
8.b. Remove existing hierarchy
9. Associate the IP-XACT memory maps with the SoC component instances
10. Dump out the C Model for the entire design
11. ...
ReliaFree is a Python and PyGTK based suite of tools to assist in Reliability, Availability, Maintainability, and Safety (RAMS) analyses. ReliaFree is intended to be an Open Source alternative to proprietary RAMS analyses solutions.