Open Source Python Electronic Design Automation (EDA) Software

[ENG] Mod FreeCAD-PCB allow you to import PCB boards to FreeCAD. Scope of mod: - support for many different layers, - possible to choose colours, transparency and names for each layer, - mod allows you to import IGES models with colours, - possible to show holes/vias independent. [PL] Moduł FreeCAD-PCB pozwala na importowanie płytek PCB do programu FreeCAD. Możliwości modułu: - wsparcie dla wielu różnych warstw, - wyświetlanie otworów, przelotek niezależnie od siebie, - możliwość wyboru koloru, przeźroczystości oraz nazwy dla poszczególnych warstw, - importowanie modeli zapisanych w formacie IGS wraz z kolorami. ***** Supported software: - Eagle (*.brd) - Razen (*.rzp) - FreePCB (*.fpc) - gEDA (*.pcb) - FidoCadJ (*.fcd) - KiCad (*.kicad_pcb) - IDF v2/v3 Requirements: FreeCAD >= 0.14 Project forum: https://sourceforge.net/p/eaglepcb2freecad/forum/

naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information

An object-oriented Python Interface to Frontline PCB's Genesis 2000 CAD/CAM/CAE system.

This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.

pyGerber2Gcode is a Pyhon based simple Gerber to G-code converter.

MyHDL is a Python package for using Python as a hardware description and verification language.

a transmission line impedance calculator

A small Python utility used to manage multiple concurrent installations of Genesis 2000.

The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.

1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database with advance queries 8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning 8.a. Insert new hierarchy 8.b. Remove existing hierarchy 9. Associate the IP-XACT memory maps with the SoC component instances 10. Dump out the C Model for the entire design 11. Glue-Logic insertion 12. Spare port insertion across hierarchies 13. Automatic creation of the top module and it's ports based upon specified rule 14. Creates stub module

SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools. If an error is detected in any of the project files during elaboration or simulation, a message is displayed in the console indicating the type and location of the error, allowing the user to quickly resolve it.

Banyan is an enterprise class, web based, information management system that helps people work collaboratively to solve complex problems. Banyan increases project performance and reduces risk through the power of collaborative clear thinking.

Blitzer is a simple tool for driving the SX-Blitz microcontroller programmer from Parallax. There is now a version for PalmOS devices.

Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material.

Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.

FXPyTurns-n-Layers is a graphical transformer and induction coil design aid. The application performs the physical design of the coils for transformer and induction coils to determine: the length/weight of wire required to wind a coil with the specified

GLogic is a logic gate simulator for linux and an adaptation of the gLogic package....

Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.

A clearing house for various pieces of open source software which use the GenCAM data format for input or output of electronic interconnect (PWB, PCB, PWA, PCA) information.

GerbTool is a set of tools for modifying gerber and excellon drill files. GerbTool can be used to tile multiple gerber files as a single job, and can be run interactively or in batch mode.

This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support. ipxact2verilog - Generate Verilog module from IP-XACT definition ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition verilog2ipxact - Generates IP-XACT definition from Verilog modules vhdl2ipxact - Generates IP-XACT definition from VHDL source ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL validateipxact - IP-XACT Linting tool

JSalesman is a very efficient Travelling Salesman problem solver that produces high-quality outputs. JSalesman uses hierarchial and multi-level approaches to solve the problem fast.

In electrical engineering, AC circuits are often used in the design process. However, deriving the gain, input impedance or what have you is tedious and error prone. LaSolv takes a SPICE like description of your circuit and solves for whatever parameter you specify- voltage gain, trans-impedance, input impedance, etc.

Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.