Search Results for "simulation software"
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Showing 3 open source projects for "simulation software"
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Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
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A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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