Digital Circuits Design and Simulation
TimingEditor is a tool to graphically draw and edit timing diagrams.
Free converters across IP-XACT Verilog VHDL Liberty SystemC
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
JQM - Java Quine McCluskey for minimization of Boolean functions.
Community driven PCB Layout and Schematic capture software
Simple and intuitive 2D vector drawing for electronics and not only.
Electronic design and programming tools suite like Eagle, MpLab
A graphical Finite State Machine (FSM) designer.
An HDL alternative to PCB graphical schematic capture tools.