Showing 6 open source projects for "api code generator"

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  • 1

    AUDio MEasurement System

    PC based Oscilloscope and Spectrum analyzer using sound card

    AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md
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    Downloads: 63 This Week
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  • 2

    System Verilog Parser IEEE 1800 LRM

    IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API

    This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the...
    Downloads: 0 This Week
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  • 3
    XOR Tree Generator
    Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
    Downloads: 0 This Week
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  • 4
    JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
    Downloads: 0 This Week
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  • 5
    PikLoops is a simple KDE program used to generate assembly time delays for Microchip microcontrolers using Microchip instructions.
    Downloads: 0 This Week
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  • 6
    vMAGIC
    vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
    Downloads: 0 This Week
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