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  • 1
    Kactus2

    Kactus2

    Kactus2 is a graphical EDA tool based on the IP-XACT standard.

    Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at...
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    Downloads: 11 This Week
    Last Update:
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  • 2
    vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
    Downloads: 0 This Week
    Last Update:
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  • 3
    SVEditor
    SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.
    Downloads: 1 This Week
    Last Update:
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  • 4
    dvkit

    dvkit

    Eclipse-based IDE for design verification tasks

    DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
    Downloads: 2 This Week
    Last Update:
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  • 5
    Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
    Downloads: 2 This Week
    Last Update:
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  • 6
    TimeDoctor
    TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.
    Downloads: 3 This Week
    Last Update:
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  • 7
    Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
    Downloads: 0 This Week
    Last Update:
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  • 8
    This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.
    Downloads: 0 This Week
    Last Update:
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  • 9
    Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.
    Downloads: 0 This Week
    Last Update:
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  • 10
    Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
    Downloads: 0 This Week
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  • 11
    A brand-new powerful major mode for editing verilog sources in Emacs.
    Downloads: 1 This Week
    Last Update:
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  • 12
    Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
    Downloads: 0 This Week
    Last Update:
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  • 13
    mcuStudio is a development environment for Microcontrollers. It's based on Eclipse (plugin). The aim is to provide a high quality development environment for electronics. First editions will target Microchip Pic mcu's. Other mcu will be supported later.
    Downloads: 0 This Week
    Last Update:
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  • 14
    IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.
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    Downloads: 2 This Week
    Last Update:
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  • 15
    PCB-Tools is a system independent, a Java programmed Eclipse-RCP application for developing circuit diagrams and printed circuit boards. It uses Eclipse Graphical Editor Framework (GEF) to draw diagrams and layouts.
    Downloads: 0 This Week
    Last Update:
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  • 16
    This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).
    Downloads: 0 This Week
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