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SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
C++ templates with generic nonlinear optimization algorithms
Highly tunable, simple to use collection of the templates, containing a set of classes for solving unconstrained large scale nonlinear optimization problems. Currently it contains:
-- Limited Memory Quasi Newton (L-BFSG)
-- BFSG
-- Conjugate Gradient
-- Gradient Descent
-- Wolf condition Line Search
-- Backtracking Line Search
-- Exact Golden Search
-- Golden Search with Wolf condition
We also distribute a set of tests with the library.
C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.
GNU PIC LIBRARY PROJECT
The interest of this project is to develop a set of Libraries that are released in LGPL License to use to PIC microcontroler programming.
Then any program resulted by this use would be a proprietary or free softwares.
The purpose of the project is to design a methodology for making Application Specific Instruction set Processors. The project is a part of the Embedded Systems project in IIT-Delhi