Search Results for "developers console"

A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.

NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the...

ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

"kdiv" is a generator of routines for optimized division by an integer constant based on the work presented in H.S. Warren's "Hacker's Delight". "kdiv" can be used to emit a generic assembly or C implementation of (signed/unsigned) division.

It is a software to program ISP based 8051 controllers(89SXX) on Linux. The software decodes the hex file entered from the command line and send it to controller's flash memory using PC's parallel port.The hardware connections are very minimal.

"mprfgen" is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.

The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.

This project aims to develop an opensource software with an attractive and efficient GUI which allows to design linear electronic circuits and to characterize existing ones.

QConsole is a custom Qt widget implementing a standard console to be inherited to support a specific scripting language or shell, and then embedded in any Qt application. As example, a Tcl console (QtclConsole) is provided for use in EDA applications

vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.

Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.

Program Avr Linux Manager, to prosty interfejs dla programów avr-gcc oraz avrdude. Umożliwia łatwą kompilację i programowanie mikrokontrolerów.

Projeto para controle da porta paralela em Linux. Este projeto pode ser utilizado como integrador em projetos de robotica ou automação industrial. Funciona na console e permite integração com diversas linguagens como java/php/c++ entre outras.

VSYML is an automated symbolic simulator for VHDL designs.

CC2430 Flash programmer and simple debug interface with NoICE support. It uses USB interface to communicate with the target CC2430 over debug interface. To install on linux do: svn co https://ccflasher.svn.sourceforge.net/svnroot/ccflasher/trunk ccfl

F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.

Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.

YAPI (Y-chart Application Programmers' Interface aka Yet Another Programmers' Interface) is a C++ library for writing (Kahn) Process Networks.

Extensions to the circuit simulator Ngspice. One extension is the integration of the next generation build system SCons.

Programmer for Atmels 8051 devices, parallel Flash and E2PROM memories and etc.

PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

This project aims at using the Artificial Intelligence (AI) algorithm called the Genetic algorithm to solve the problem of placement in the FPGA circuits.

Modular system to emulate any digital system you care to imagine. Add modules for input and output devices, processors, microcontrollers, etc.