Search Results for "qt-eclipse-integration"

...Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database with advance queries 8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning 8.a. Insert new hierarchy 8.b. ...

SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.

DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.

Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).

...However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.

PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. ...

Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.

Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.

mcuStudio is a development environment for Microcontrollers. It's based on Eclipse (plugin). The aim is to provide a high quality development environment for electronics. First editions will target Microchip Pic mcu's. Other mcu will be supported later.

IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.

mCon aims to be platform independent, complete IDE for micro controller development. The project will use Eclipse as its foundation and the initial goal is to support development for the microchip PIC microcontrollers.

PCB-Tools is a system independent, a Java programmed Eclipse-RCP application for developing circuit diagrams and printed circuit boards. It uses Eclipse Graphical Editor Framework (GEF) to draw diagrams and layouts.

This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).