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This project provides a analog / mixed signal IC schematic capture and layout tool with the accompanying netlisters, simulators, and verification tools.
WARNING: This project is under hard development and not intended for productive use yet but only for discussion.
jCLS helps to create and maintain fine detailed component libraries for EDA tools like Altium Designer. It provides tools for data generation for masses of single parts from only the most necessary informations. Having good maintained and rich described and voluptuous detailed component libraries needs normally masses of time, work and discipline. jCLS comes here to save you from the molesting parts of this job.
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A Java Native Interface (JNI) library suitable for communicating with a range of USB interface chips from FTDI via the D2XX driver.
It currently supports OS X 10.10+ and Windows 7/8 x64.
On OS X, the 64 bit JVM is supported. On Windows, support is limited to the 64 bit JVM (Java 1.8 is now 64 bit).
Version 1.0
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- Java 8
- SPI support and sample (via MPSSE)
JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
This is a very powerful Schematic and PCB layout tool for Engineer
...Coming version will add the SPICE features as well as the 3D model.
This tool is target for single user, so all the things such as Schematic, PCB layout, SPICE model, 3D models are all combined into a single project file "*.prj" in ZIP file format. Anyone should able to explore and see the structure of files using any zip tool.
Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).
An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities.
This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project has been moved to bitbucket.org:
- https://bitbucket.org/vahidi/jbdd/wiki/Home
- https://bitbucket.org/vahidi/jdd/wiki/Home
It includes two libraries for working with decision diagrams:
- JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy
- JDD: a native Java library supporting BDD, Z-BDD
Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool .
Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
Remote Control for Embedded Device
Provide an user interface for a embedded device on a PC or a mobile phone.
Communication through RS232, USB, TCP_IP, Bluetooth...
Power consumption analysis tools for embedded systems. MARTE to AADL model transformation with ATL for tools interoperability. More info on the project at http://sourceforge.net/apps/trac/lab-sticc/
Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported.
Project branch continues to evolve: https://github.com/gburdell/nldb
including addition of tclsh UI.
The SESAME (Simulation of Embedded System Architectures for Multilevel Exploration) software system is an embedded system co-simulation environment and research tool which implements the ideas of the SESAME project at the University of Amsterdam.
The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.
Visually build and simulate boolean logic circuits
Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality.
NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox
The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
mCon aims to be platform independent, complete IDE for micro controller development. The project will use Eclipse as its foundation and the initial goal is to support development for the microchip PIC microcontrollers.
GNU PIC LIBRARY PROJECT
The interest of this project is to develop a set of Libraries that are released in LGPL License to use to PIC microcontroler programming.
Then any program resulted by this use would be a proprietary or free softwares.
vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.
This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).