Search Results for "qgis-osgeo4w-2.6.1-1-setup"
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Showing 103 open source projects for "qgis-osgeo4w-2.6.1-1-setup"
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Repfabric is a customer relationship management (CRM) software designed specifically for multi-line sales teams (i.e. reps, distributors, wholesalers, dealers, and manufacturers). It streamlines and simplifies the sales process by providing deep integration with email, contacts, calendars, and deal tracking. The platform enables users to track commissions from CRM to sale, make updates directly from mobile devices, and document sales calls using voice-to-text features.
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MATRIX 1.4 VII
MATRIX 1.4 Audio Power Amplifier Platform Release VII
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VeroRoute
Qt based Veroboard, Perfboard, and PCB layout and routing application
Cross-platform software for producing Veroboard (stripboard), Perfboard, and 1-layer or 2-layer PCB layouts. Automatically prevents short-circuits and checks for open-circuits. Pre-compiled versions available for MS Windows and 64-bit Linux Mint 20.3 (should also run on other 64-bit Linux systems that are based on Debian and support Qt version >= 5.12.8). Android APK available (tested on Android 7 and Android 10) and requires device resolution of at least 1280x800. -
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database... -
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jCLS
The Component Library Sorcerer
WARNING: This project is under hard development and not intended for productive use yet but only for discussion. jCLS helps to create and maintain fine detailed component libraries for EDA tools like Altium Designer. It provides tools for data generation for masses of single parts from only the most necessary informations. Having good maintained and rich described and voluptuous detailed component libraries needs normally masses of time, work and discipline. jCLS comes here to save you... -
We design our technology to make workforce management easier. APS offers core HR, payroll, benefits administration, attendance, recruiting, employee onboarding, and more.
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
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ePnR
ePnR is an IC block standard cell placement & routing tool
ePnR is a simple Integrated Circuit (IC) block standard cell placement & routing tool. ePnR currently supports only circuit blocks using equal height standard cells arranged in one or more channels of user configurable length. Standard cells are described in a simple text based library (compliant with eLogSim). Placement follows initially the cell call order in the SPICE like circuit input netlist. However, a placement optimization, aiming at minimum weighted accumulated wire length... -
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents...
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JQM Java Quine McCluskey
JQM - Java Quine McCluskey for minimization of Boolean functions.
Java Quine McCluskey implements the Quine McCluskey algorithm with Petrick’s Method (or the method of prime implicants) for minimization of Boolean functions. This software can be used both for learning and solving real problems. As a learning/teaching tool, it presents not only the results but also how the problem was solved as well as how to use Karnaugh Maps to solve the problem. Up to sixteen functions of sixteen variables can be minimized. A graphical interface is provided for entering... -
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Plan more projects with Worksection. Use Gantt chart and Kanban boards to organize your projects, get your team onboard and assign tasks and due dates.
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TinyCAD is a program for drawing electrical circuit diagrams commonly known as schematic drawings. It supports standard and custom symbol libraries. It supports PCB layout programs with several netlist formats and can also produce SPICE simulation netlists. It is also often used to draw one-line diagrams, block diagrams, and presentation drawings. The source code for TinyCAD is now on GitHub: https://github.com/matt123p/TinyCAD Online documentation can be found here: https://github.com...
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eLogSim
Digital circuit simulator
eLogSim is an event driven, 4-level (0,X,1,Z) digital circuit simulator. It uses a test oriented stimulus approach and offers a statistical (or exhaustive if it makes sense) fault simulation option. eLogSim has a simple GUI and is pre-compiled for Ubuntu 20, Mint 20, CentOS 8, openSUSE 15, FreeBSD 12, Solaris 11, Windows 10/11 & Raspbian/Raspberry PiOS Buster (32/64bit) & Ubuntu-MATE 20.04 (64 bit) operating systems. Cross platform & -network, concurrent fault simulation now available... -
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Mod Direct Panoramic Spectrum Analyzer
Mod Direct Panoramic Spectrum Analyzer
1. Added the ability to directly work with the chip (parameter "settings.ini" - Direct=1). 2. The possibility of cyclic writing/recording from realtime to a file and subsequent playback from it is added (double click of the left mouse button anywhere in the top spectrogram). The size of the MB file is specified in the settings file (Cyclic file size=100). -
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Kicad shematic library manager
Kicad shematic library manager
This is a first release of kicad schematic library manager. With this manager new schematic symbols can be created and or modified using spread sheet. The informations of component as description, documentation etc. can be modified as well. This manager enables moving components from one library to another one. The project source sode is hosted on: https://github.com/Filip83/kicad-lib-utils -
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GDS2HFSS is a circuit design utility to convert 2-dimensional layout file in GDS stream format into a 3-dimensional structure in electromagnetic (EM) simulator - ANSYS High Frequency Structure Simulator (HFSS).
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SOCGEN is a collection of tools that will help create digital components/ip_cores and then integrate them into a "System on a Chip"(SOC) for use in ASIC or FPGA designs.
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags... -
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... like: 1.- You can double-click a cable in the diagram and define the wiring of that cable in a pop-up dialog. 2.- Also the parts have properties that define all the connector Jacks / Plugs (J/P) they have (e.g., J1 or P1 would appear at the part). 3.- Rack lay out tool. You can associate each part with its rack view equivalent. For example: you can associate a part that is a Server with a rack part of 4U height to place at the rack This software produces block diagrams and wiring sheets
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STANTOR
Scada for Home Automation
Stantor is a SCADA for home automation/domotic project. It drives : k8061-K8055(USB), K8000(I2C), Arduino Mega and Uno, X10, 1-Wire, electricity meters, Webcam (motion), infrared remote controls. It uses WEB browser, smartphone, xHTML, SOAP, Websocket, HTML5 Apache, mySQL, PHP, javascript and Ajax. Stantor allows control of electrical equipments like boilers, shutters, lamps, pumps, etc...connected to the 220V/110 VAC. Gathering information of various kinds such as temperature, light... -
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Electronic Component API
Search electronic components, datasheets, stock, price, alternatives
... for component information in a variety of ways, including searching via description or part number. Queries to the Ciiva API return one or more data objects which contain information on manufacturer and supplier components, such as lifecycle, compliance, pricing, availability, substitutes/alternatives, datasheets, and more. -
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Spider PCB
Hierarchical Schematic and PCB
... channel of the equaliser, then go up one hierarchical level and lay out 1 sound channel, using your single-band equaliser 16 times, with the only difference being the component values. You can then go up one hierarchical level more to lay out the 5 sound channels, add some headers and a power supply circuit, and another to panellise the PCB's for production. No copying and pasting. No trouble editing a mistake later. This is the idea behind Spider PCB. For more information, read the Wiki. -
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gencir
Evolvable Circuits
Evolvable Circuits -
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PLLSim
Simulation Tool for Phase-Locked Loops
A simulation tool for Phase-Locked Loops with charge pump phase detectors. The tool simulates phase and frequency steps with continous reference and random bit stream reference for data clock recovery. -
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The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.
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Cost Modeling Tool for SoC Testing
Matlab based Cost Modeling Tool for SoC Testing
Testing complex VLSI circuits, where the whole system is integrated into a single chip called System on Chip (SoC) is very challenging due to its complexity. A SoC design consists of multiple IP cores (logic, memory, analog, high speed I/O interfaces, RF, etc.) which generally use different technologies. SoC test is the appropriate combination of test solutions associated with individual cores. Cost modelling plays a vital role in reduction of test cost and time to market. This Matlab based... -
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CAD2Board
is a Qt program to generate SMD chip shooter code
Still struggling with Excel to setup your pick and place machine ? Cad2Board reads component mounting information from Eagle, Altium Designer and Mentor Expedition PCB designs. Component or component groups can be assigned to feeder slots by drag and drop. Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a seperate...