Search Results for "new open lms"

Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at https://github.com/kactus2/kactus2dev/issues For...

UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So...

This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.

This project is dedicated to the optimization of (any) electrical and electronic circuits and components using evolutionary and heuristic algorithms incorporated with SPICE simulators (such as HSPICE, ngSPICE, etc.). We provide Optimer, which is a user graphical interface for circuit design and optimization. Website: https://www.circuitoptimization.com/ E-mail: contact@circuitoptimization.com/

kicad StepUp: a new approach to export kicad board and modules in STEP AP214 (with colors). With kicad StepUp, it is possible to work in kicad EDA with the same component model data available in the STEP AP214 3D format, and obtain a 3D STEP AP214 model of the pcb board and a complete board assembles with electronic modules, to be used for MCAD interchange. The accurate 3D visualization of components on board assembles in kicad 3dviewer, is maintained in the same accuracy and aspect in STEP...

This is a first release of kicad schematic library manager. With this manager new schematic symbols can be created and or modified using spread sheet. The informations of component as description, documentation etc. can be modified as well. This manager enables moving components from one library to another one. The project source sode is hosted on: https://github.com/Filip83/kicad-lib-utils

NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.

Current work at: https://github.com/jcampos73/DraftCable WARNING: version 1.0.94 previous to 2016-01-22 has a BUG! Download again! Min. Req: Win XP SP3 If you get missing mfc120.dll install vcredist_x86.exe at prog folder CAD design tool for electrical and block diagrams with net list compilation. Tool for creating new parts included. DO NOT lose time copy and pasting cable datasheet. This program, unlike MS Visio or other generic tools, has specific business funcionalities like: 1.- You...

ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

... project file. Succeeding PCB revisions what contain redesign changes can be merged with existing project setup data. Inconsistencies are highlighted to solve them by new assignements and unused feeders can be cleaned up with a single push. Finally a machine program is generated in Heeb HE50 format and downloaded to the machine interface.

The Virtual Electronics Library, or VE-Lib, is a C++ library used to easily add electronic simulation in your programs. It makes use of the scripting language Lua to easily add new components like new resistors and microchips.

GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.

A brand-new powerful major mode for editing verilog sources in Emacs.

Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.

The official repository of JCSim is now hosted by github at https://github.com/almejo/jcsim JCSim is a fully functional Digital Circuit simulator written in Java. You can create and simulate simple (and not so simple) circuits in an easy way. It includes a basic set of gates, simple creation of new gates and simulation.

Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.