Search Results for "car simulation source code"
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Showing 19 open source projects for "car simulation source code"
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PICSimLab - Prog. IC Simulator Lab.
PICSimLab is a realtime emulator for PIC, Arduino, STM32, ESP32, ...
...PICSimLab has integration with MPLABX/Arduino IDE for programming the microcontroller's boards. As the purpose of PICSimLab is to emulate real hardware it does not have any source code editing support. For code editing and debugging the same tools used for a real board should be used with PICSimLab, such as MPLABX, Arduino IDE, or VSCode with PlatformIO. PICSimLab supports several devices (spare parts) that can be connected to the boards for simulation. Such as example LEDs and push buttons for simple outputs and inputs and some more complex ones like the ethernet shield w5500 for internet connection or the color graphic display ili9340 with touchscreen. ... -
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SimFPGA
VHDL Verification and Simulation Tool
SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools. ... -
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QTronics ToolSet
Includes tools for performing electronic calculations.
This program contains many tools for you to perform detailed electronic calculations. Ohms, Kirchhoff, Parralel Res., Voltage Divider, Wheatstone, Reistor Color, Zener diode, LED resistor, capacitor, inductor, transformer, capacitive reactance, Transformerless adaptor, R-C Time calculator, Flip-Flop, NE555 calculator, TL431 calculator, 78XX, LM317, Current Limiter, Transistor Regulator, Current Mirror, Battery charge calculations, transistor calculator, mosfet, pass filters, opamp,... -
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
v21.06.018 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux... -
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SimulIDE
Real Time Electronic Circuit Simulator.
Real Time Electronic Circuit Simulator. Include PIC, AVR and Arduino simulation. Code Editor & Debugger for Arduino, GcBasic, PIC asm, AVR asm. Downloads: https://simulide.com/p/downloads/ WebSite: https://simulide.com Forum: https://simulide.com/p/forum/ Patreon: https://www.patreon.com/simulide AVR simulation provided by simavr: https://github.com/buserror/simavr PIC simulation provided by GpSim: http://gpsim.sourceforge.net/ -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So, the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave). -
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TinyCAD is a program for drawing electrical circuit diagrams commonly known as schematic drawings. It supports standard and custom symbol libraries. It supports PCB layout programs with several netlist formats and can also produce SPICE simulation netlists. It is also often used to draw one-line diagrams, block diagrams, and presentation drawings. The source code for TinyCAD is now on GitHub: https://github.com/matt123p/TinyCAD Online documentation can be found here: https://github.com/matt123p/TinyCAD/wiki
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eLogSim
Digital circuit simulator
eLogSim is an event driven, 4-level (0,X,1,Z) digital circuit simulator. It uses a test oriented stimulus approach and offers a statistical (or exhaustive if it makes sense) fault simulation option. eLogSim has a simple GUI and is pre-compiled for Ubuntu 20, Mint 20, CentOS 8, openSUSE 15, FreeBSD 12, Solaris 11, Windows 10/11 & Raspbian/Raspberry PiOS Buster (32/64bit) & Ubuntu-MATE 20.04 (64 bit) operating systems. Cross platform & -network, concurrent fault simulation now available. Commented, easy-to-compile source-code included as well. -
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Electronic Circuit Optimization
Optimer: a SPICE base electrical/ electronic circuit optimization tool
This project is dedicated to the optimization of (any) electrical and electronic circuits and components using evolutionary and heuristic algorithms incorporated with SPICE simulators (such as HSPICE, ngSPICE, etc.). We provide Optimer, which is a user graphical interface for circuit design and optimization. Website: https://www.circuitoptimization.com/ E-mail: contact@circuitoptimization.com/ -
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GNUSim8085 is a simulator and assembler for the Intel 8085 Microprocessor. For downloading latest release please head to the website - https://gnusim8085.github.io/ For source code - https://github.com/GNUSim8085/GNUSim8085
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Cadence 614 Installer
Cadence 614 installing scripts with source files
this code include automation for installing Cadence614 with Calibre2011 all you need to do is to install Centos 6.5 32bit on your machine http://archive.kernel.org/centos-vault/6.5/isos/i386/CentOS-6.5-i386-LiveCD.iso and the scripts will do the rest -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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OpenETran
Electric power system transient simulator
During the period from 1990 through 2002, EPRI funded the development of a Lightning Protection Design Workstation (LPDW), which was used by many utilities to assess the lightning performance of distribution lines. Since about 2002, this program has not been available. EPRI decided to release the simulation kernel of LPDW under an open-source license (GPL v3), so it may be incorporated into IEEE Flash and other projects. OpenETran can presently simulate multi-conductor power lines, insulators, surge arresters, non-linear grounds, and lightning strokes. It efficiently calculates energy and charge duty on surge arresters, and iterates to find the critical lightning current causing flashover on one or more phases. ... -
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ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.
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UVE
Unified Verification Environment
The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology. UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of...
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