Search Results for "eda tool"

DLD V 2.0 Released Digital Logic Design is a Software tool for designing and simulating digital circuits. It provides digital parts ranging from simple gates to Arithmetic Logic Unit. You may start your circuit from simple gates and flipflops and keep on converting them into ICs. These ICs, later on, may be incorporated into other circuits to built more complex circuits like CPU. You may even use SOP expressions to generate digital circuits in IC form. You can use this software to...

What is DSPICE? DSpice (Designing Circuits and Simulation by SPICE) is an open-source tool designed to streamline the modeling of analog components and the simulation of electronic circuits. It leverages ngspice (the open-source successor to the classic SPICE engine) as its core simulation backend. The main objectives and features of DSpice are: . Custom Modeling: Creating new SPICE models for various electrical components. . Symbol Design: Designing and managing custom schematic...

Java Quine McCluskey (JQM) implements the Quine-McCluskey algorithm with Petrick’s Method for minimizing Boolean functions. Designed for both education and industrial application, it handles up to 16 variables and functions. Uniquely, JQM bridges the gap between theory and practice: it visualizes the solution process with generated Karnaugh Maps for students, while supporting PLC engineers by exporting results to Structured Text (ST) and Ladder Diagram (LD). The software includes a GUI for...

ePnR is a simple Integrated Circuit (IC) block standard cell placement & routing tool. ePnR currently supports only circuit blocks using equal height standard cells arranged in one or more channels of user configurable length. Standard cells are described in a simple text based library (compliant with eLogSim). Placement follows initially the cell call order in the SPICE like circuit input netlist. However, a placement optimization, aiming at minimum weighted accumulated wire length, by...

This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.

tkCybernetics is a small grafical tool for rapidly setting up simulations of simple cybernetic systems. It was designed for didactic purpose but might be useful for the quick test of some circuit too.

A java based digital logic simulator, designed to be used as an educational tool. uses a GUI to allow users to quickly and easily create and visualise circuits from simple components. User can create custom components