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XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for...
Tools and Z80 engine for creating adventure games. (RUST)
This is an exercise in some advance programming topics using a text adventure as the central result. This originally began as a project to recreate an old BASIC text adventure, on the ZX Spectrum, using Z80. After developing a very simple byte code VM to handle the game interactions, I realised that there was an opportunity to use some more advance techniques, which in turn can lead to some PC based tools.
A real time inference engine for temporal logical specifications
A real time inference engine for temporal logical specifications, which is able to acquire, process and generate any binary or real signal through POSIX IPC, files or UNIX sockets. Specifications of signals and dynamic systems are represented as special graphs and executed in real time, with a predictable sampling time of few milliseconds. Real time signal processing, dynamic system control, state machine modeling and logical property verification are some fields of application of this...
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A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
A new Language, Compiler, and IDE for developing PORC for Symitar systems. The PowerPlus language gives you locals, parameters, return values, and many other C/C#/JavaScript like features. The PwrIDE environment is an updated RepDev/POS replacement.
Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.