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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators.
Repository migrated to:
https://github.com/Qucs/ADMS
For checkout do:
git clone https://github.com/Qucs/ADMS.git
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI.
All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead
Project2306 IDE :
Application pour la programmation de Microcontroleurs et d' Application Electronique
Project2306 IDE :
for All whom want to Create and Develop on Embed Platform
Software as Programming Tools suite and PCB Design
Planned...
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files.
Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.