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    Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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    Software PLC using Instruction List language as described in IEC-1131-3 for RT-Linux. This project is a part of the diplomas thesis on CTU FEE (http://dce.felk.cvut.cz)
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