Search Results for "scientific plotting software"
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Showing 147 open source projects for "scientific plotting software"
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TFEL/MFront
TFEL/MFront introduces DSLs based on C++ to handle material knowledge
The TFEL library is a collaborative effort of the French Atomic Commission and Électricité de France. TFEL mostly includes the MFront code generator. MFront is based on C++ and provides several domain specific languages which were designed to simplify the implementations of new material properties, mechanical behaviours and simple material models. A particular focus was made on mechanical behaviours which are by essence more complex and may have significant impact on the numerical... -
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Community Z Tools
Tool support for the Z formal notation
Community Z Tools Project (CZT): Tools for editing, typechecking and animating Z specifications and related notations. Includes a Java framework for building formal methods tools. NOTE: development of CZT has now moved to GitHub: https://github.com/community-z-users/czt -
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GCBASIC is an open-source BASIC compiler for 8 bit Microchip PIC, Atmel AVR legacy, AVRDx and LGT microcontrollers. See https://ko-fi.com/post/The-Story-of-GCBASIC-Making-Microcontroller-Progr-D1D319SJ72 for story of GCBASIC. This is a continuous release project. The latest release is always available. This will give you the most complete development toolchain to create and program 8-bit PIC, AVR and LGT microcontrollers. We have added new capabilities that make GCBASIC the...
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COBOL copybook to XML converter
Converts cobol copybooks to Xml/Java objects
CB2XML (CopyBook to XML) is a COBOL CopyBook to XML converter written in Java and based on the SableCC parser generator. This project includes utilities to convert an XML instance file into its COBOL copybook equivalent string buffer and vice versa. Source is now available in GitHub: https://github.com/bmTas/cb2xml -
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This is an application generator for conflation algorithms in perl language. This system supports generation perl source code for a stemmer from a rule file, running a stemmer which is supported by the system, parsing a corpus file.
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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PCYNLITX
Pcynlitx is an innovative multi-thread software development platform
Pcynlitx is an innovative open-source multi-thread software development platform and it is an outcome of a scientific research study that is carried out by Erkam Murat Bozkurt who is a research engineer in ISTANBUL/TURKEY. Basically, Pcynlitx is not a threading library. Instead, Pcynlitx is a threading library generator and it produces an application specific multi-threading library specialized based on its user needs. -
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Patlac--Xml2cpp is a totally customizable code generator that generates classes (c++ for now) automatically from a xsd schema. Classes are described in google-ctemplate files and a xml options file allow precise definition of projects.
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JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
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FBtranslate chung is a program to help translation in a foreign language strings data of a freebasic program . It is written in freebasic and uses gui_chung . It extracts all strings literals of a program code into a single file, so you can translate this file with an free online translator like google translate , then rebuilds the new program with the translated text data.
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned... -
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G4LTL-ST
Generating PLC programs from formal specifications
G4LTL-ST is a standalone tool and a Java library for automatically generating industrial control software (supporting IEC-61131-3 Structure Text) from LTL or extended logic specifications. See Tutorial.txt inside the package for step-by-step instructions. For technical demails, see CAV'14 paper "G4LTL-ST: Automatic Generation of PLC Programs". The old version (G4LTL; under BSD license) is available under file\arxiv. -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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Petri-LLD is a graphical development environment for real-time automation control and is written in Java. It is based on a form of Petri net, and compiles to a number of programmable logic controller (PLC) languages as well as Java and Visual Basic.
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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ASN.1 types and codecs (BER, CER, DER) implementation in Python programming language. A collection of various ASN.1-based protocols data structures is supplied in a dedicated Python package. Project moved to GitHub: https://github.com/etingof/pyasn1
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Making the tools of annotation languages, source-to-source code transformation and code generation more useful and accessible to the developers of scientific and engineering software for high-performance computers.
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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BDM generator
C generator for binary protocol parsers
From a description of a protocol in OpenDocument format, generate a C parser for this protocol. For now supports only binary protocols with fixed-size frames (several frames can have different sizes but a frame shall always have the same size). - Verify validity of each field of a frame before validating the frame and copying its content to a destination dictionnary. Can be used to generate parsers for CAN protocols like J1939, custom serial protocols... -
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RANGE: produce random genetic transcription networks in the NEMO language, which when compiled outputs models in Systems Biology Markup Language. Generate synthetic microarray data, or use NEMO alone to SBML-ize a network, or visualize it in cytoscape.
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The target system of this project is to develop mathematically efficient program code generator from cellml like biological models described by mathematical markup languages.
