Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
https://github.com/chiphackers/covered
A cross platform Http web server developed using C++.
Agile methodology with emphasis on :-
1. Good Design
2. Object Oriented Programming
3. Refactoring
4. Static/Dynamic Analysis, Unit-testing, Code Coverage
5. Software Engineering best practices.
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