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    Covered
    Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
    Downloads: 5 This Week
    Last Update:
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  • 2
    Cov is a code coverage tool to get your code coverage after your runuing some steps for your programs.It is based on llvm(Low Level Virtual Machine,http://llvm.org/).Now,it's only a begining,so welcome anybody to join in.
    1 Review
    Downloads: 0 This Week
    Last Update:
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  • 3
    STUBborn C is a tool that allows you to create a module test framework for SW modules developed in C. The framework includes: Stubs needed to link the module; A sample Makefile to build, run tests and check code coverage; Test templates using CUnit.
    Downloads: 0 This Week
    Last Update:
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  • 4
    Javelina is an advanced code coverage tool that uses dynamic instrumentation to minimize the overhead for collecting coverage data. Additionally, Javelina allows the application of logical operations to code coverage data.
    1 Review
    Downloads: 0 This Week
    Last Update:
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