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Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
xswifs stands for: cross SoftWare Interfaces.
This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
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Pancham is an IP core that implements the MD5 message digest algorithm. It is written in Verilog and comes with a testbench. It will be portable across multiple simulators and will be synthesizable.