Showing 5 open source projects for "python verilog"

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  • 1
    XLS

    XLS

    XLS: Accelerated HW Synthesis

    XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA...
    Downloads: 5 This Week
    Last Update:
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  • 2
    wxMEdit

    wxMEdit

    wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit

    •Added automatically checking for updates •Added bookmark support •Added right-click context menu for each tab •Added purging histories support •Added selecting a line by triple click •Added FreeBASIC syntax file •Added an option to place configuration files into %APPDATA% directory under Windows •Improved support for Find/Replace •Improved Mac OS X support •Improved system integration under Windows •Improved encoding detection result •Improved Hex editing support •Added more...
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    Downloads: 189 This Week
    Last Update:
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  • 3
    Qfsm

    Qfsm

    A graphical Finite State Machine (FSM) designer.

    A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
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    Downloads: 14 This Week
    Last Update:
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  • 4
    naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information
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    Downloads: 0 This Week
    Last Update:
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  • 5
    Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
    Downloads: 1 This Week
    Last Update:
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