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This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.
The TclPro tool set includes a graphical debugger, a static code checker,
a wrapper to generate stand-alone executables, a "compiler" that
writes out Tcl byte codes, and a loader that reads byte codes.