Showing 2 open source projects for "64 bit zorin"

View related business solutions
  • Top-Rated Free CRM Software Icon
    Top-Rated Free CRM Software

    216,000+ customers in over 135 countries grow their businesses with HubSpot

    HubSpot is an AI-powered customer platform with all the software, integrations, and resources you need to connect your marketing, sales, and customer service. HubSpot's connected platform enables you to grow your business faster by focusing on what matters most: your customers.
  • Simplify Purchasing For Your Business Icon
    Simplify Purchasing For Your Business

    Manage what you buy and how you buy it with Order.co, so you have control over your time and money spent.

    Simplify every aspect of buying for your business in Order.co. From sourcing products to scaling purchasing across locations to automating your AP and approvals workstreams, Order.co is the platform of choice for growing businesses.
  • 1
    RedtDec

    RedtDec

    RetDec is a retargetable machine-code decompiler based on LLVM

    The decompiler is not limited to any particular target architecture, operating system, or executable file format. ELF, PE, Mach-O, COFF, AR (archive), Intel HEX, and raw machine code supported. 32-bit: Intel x86, ARM, MIPS, PIC32, and PowerPC 64-bit: x86-64 supported. Demangling of symbols from C++ binaries (GCC, MSVC, Borland). Reconstruction of functions, types, and high-level constructs. Output in two high-level languages: C and a Python-like language. Generation of call graphs, control-flow...
    Downloads: 40 This Week
    Last Update:
    See Project
  • 2

    UniSIMD-assembler

    SIMD macro assembler unified for ARM, MIPS, PPC and x86

    ... and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. See README file.
    Downloads: 0 This Week
    Last Update:
    See Project
  • Previous
  • You're on page 1
  • Next