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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files.
Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.
This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
A code template tool for VHDL development which outputs to the clipboard - this means it can be used with any tool. Written in Ada, using GTK. Runs on Windows XP and Linux with common source code
Free diagnostic script reveals configuration issues, error patterns, and security risks. Instant HTML report.
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