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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic...
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Typelib Wizard is a tool to improve your COM/COM+/COMTI experience as it allows you to navigate through TLB structure.
It is a kind of Object Browser with steroids.
Full parameter test of x86 CPU's memory subsystem, including L1/L2 cache size/block size/association/write policy, L1/L2/memory bandwidth, BTB depth, RAS depth, TLB size/association and more. Best for architecture understanding purpose.