Search Results for "modelsim"
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Showing 6 open source projects for "modelsim"
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32-BIT GENERAL PURPOSE INTEGER PROCESSOR
Simple single cycle processor based on triadic Harvard architecture.
A 32-bit MIPS simple single cycle processor based on triadic Harvard architecture with a RISC-like ISA. This project is done in Cairo University-Faculty of Enigneering, Electronics and Electrical Communication department (EECE-2017) -
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VgaSim simulates a VGA screen connected to your VHDL and VeriLog design. Simulated signals from your desing will handle the virtual VGA screen such as it were real. VgaSim works with VHDL and VeriLog simulators such as ModelSim and GHDL.
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HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
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This project aims to provide a Tcl/Tk compile script for ModelSim, a VHDL simulator. It shall comprise easy (re-) compilation and simulation of VHDL models. Furthermore, the Tcl/Tk script shall be highly configutable to easily adopt it to new projects.
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Generic Safety CPU test framework
Generic CPU test programs and a testbench
...Additional to the test programs, the project includes a test framework consisting of a program calling the sub-test-programs and a TCL script which injects faults to verify the test programs. To run the TCL script, a user has to set up a testbench with Modelsim to simulate the HDL code of a CPU. The CPU runs the test programs and the TCL script injects faults into the CPU.
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