Search Results for "approximate adder"

We provide an open-source library of approximate arithmetic modules (adders and multipliers) described using Verilog HDL. In case of usage please refer to: H. Waris, C. Wang, W. Liu, J. Han and F. Lombardi, "Hybrid Partial Product-based High-Performance Approximate Recursive Multipliers," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2020.3013977.

Using Approximate Computing, we have designed an innovative approximate adder with real-world image processing applications. The uploaded project includes its Matlab and Verilog models for result reproduction. This is an ongoing study and we aim to formally publish it for better understanding of viewers.

The "ApproxFPGAs" library contains all the RTL (VHDL) and behavioral (MATLAB) models of FPGA-based approximate adder designs presented at DATE 2018. In case of usage please refer to: B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, “DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA-Based Systems”, IEEE/ACM 21st Design, Automation and Test in Europe Conference (DATE), March, 2018.

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. ...