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Scheduler in ORC scheduled BB again, it can't keep
branch op in the last cycle. It also influences the
behavior of Cflow.
Example: main() BB231 in mcf peak mode.
Option : peak mode + -itanium2.
2003-03-17 04:06:25 UTC in Open Research Compiler - Aurora
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fixed !
2002-07-19 03:18:21 UTC in Open Research Compiler - Aurora
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PU 5, file :graphRoutines.f90
Compiler Version:
Assertion Information:
### Assertion failure at line 1713
of ../../be/cg/orc_intel/cggrp_microsched.cxx:###
Compiler Error in file graphRoutines.f90 during Multiple
Branch phase:### couldn't find bundle for slot
mask=0x10002004, stop mask=0x2 in OPSSignal:
Segmentation fault in Multiple Branch phase.Error:
Signal Segmentation...
2002-06-19 12:29:00 UTC in Open Research Compiler - Aurora
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Now after testing and triage again, the bug turns to other
phase, This is the triage result :
ORC version: ORC Compilers: Version 1.0.0 $ModifiedDate
2002.06.06.16.34.47 $
Bug:
file rectmm.o PU 0 RGN 41
phase:
reproduce under pre_glos=on & cntl_spec=on.
2002-06-09 09:12:27 UTC in Open Research Compiler - Aurora
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Compiler Version:
ORC Compilers: Version 1.0.0 $ModifiedDate
2002.06.03.17.38.37 $
Options :
O3+P+-INLINE:inline_script=scipt.peak:list+IPA
parser run failed in the second annotion round.
Bug is in 2.o which is constructed by ipa.
PU :26 free_power_tables.
phase: cross_nest_region.
Note: the option for cross nested region
-Wb,-IPFEC:glos_code_motion_across_nested_rgn...
2002-06-05 11:52:10 UTC in Open Research Compiler - Aurora
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Micro-scheduler still loss some opportunities for
bundling op. For example:
the scheduled op list:
{ .mii
ld r16=[r16]
cmp.ltu p0,p10=0,r48 ;;
nop.i
}
{ .mmb
ld8 r30=[r30]
mov r31=r8
(p8) br.cond.dpnt.few .Lt_2_26 ;;
}
Now we want to issue new op,
(p10...
2002-05-30 06:54:59 UTC in Open Research Compiler - Aurora
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After DongYuan's check ,the latency should be 3.
So, I think this bug should be closed.
2002-05-30 06:53:25 UTC in Open Research Compiler - Aurora
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I think this problem must be checked.
shr.u is multimedia instruction, it belongs
to instruction class:MMSHF. And According
to micro-architecture page 11, there is
LD+1 cycle latency between LD and MM operation.
And LD takes 2 cycle, so the latency should
be 3 cycle. And the information from knobsfile
also same as this. So, I think 3 cycle is correct.
2002-05-16 09:45:05 UTC in Open Research Compiler - Aurora
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In native build compiler testing, I found first run of
twolf O2+Profiling is caused by wrong libcginstr.a.
This library is only packed with one object file
cg_instru_lib.o. Since we use libcginstr.a which is
compiled by g++ then, twolf can pass ref test. I have
investigated some reason for it.
Reproduce
twolf flags:
orcc(O0 -g native-build) -O2 EDGE_PROFILE=INSTR...
2002-03-13 09:18:46 UTC in Open Research Compiler - Aurora
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Putting following two ops in the same cycle for wrong zero
latency given by machine model mainly causes the bug.
Example:
mov_f_ar r5 = ar.unat
st r[33] = r5
There has REGIN dependence between two ops, but the
precedent op'opcode is a pseudo opcode. So, machine model
answers latency query between two ops as zero. And micro-
sched phase will put them...
2002-01-15 06:46:05 UTC in Open Research Compiler - Aurora
