-
llrpadmin changed the public information on the LLRP toolkit project.
2009-08-05 17:50:29 UTC in LLRP toolkit
-
I may see a problem. I'm not sure which ROSpec you are using, but if it doesn't have an immediate trigger, you will need to use a START_ROSPEC message. I would not start the ROSpec until afte the ACCESS_SPEC has been enabled.
2009-07-30 15:54:25 UTC in LLRP toolkit
-
The PC bits are at word offset 1. You'd need to write a 0b0111 1000 0000 0000 (0x7800).
However, its strange that you are able to read via another protocol. Can you share the snippet of code that you use to get the EPC data out of the TagReport.
2009-07-28 20:47:03 UTC in LLRP toolkit
-
It's hard to ascertain whether we are talking about a problem with the LTK.NET or whether your tag actually currently contains a 96-bit EPC. Even if the tag is capable of containing a longer EPC, it still may be programmed with only 96-bits. Judging from the EPC value returned by the reader (3005FB63AC1F3841EC880467) this is a GTIN-96 as defined by the EPCglobal tag data standard. You need to...
2009-07-27 19:24:45 UTC in LLRP toolkit
-
The target tag mask defines the set of tags for which you want this write to apply. If you hav a specific tag you want to write, you can put the EPC value as the data and the whole value (all 1s) as the mask. If you want to write all tags, you can use "" as the mask and data (0 length).
2009-07-27 19:19:48 UTC in LLRP toolkit
-
llrpadmin made 3 file-release changes.
2009-07-24 18:32:01 UTC in LLRP toolkit
-
llrpadmin changed the public information on the LLRP toolkit project.
2009-07-24 17:54:27 UTC in LLRP toolkit
-
For any LLRP reader, you would need to add an AccessSpec that contains a write opSpec. In Gen2, the EPC memory is memory bank 1. The EPC starts at word offset 2 (bit offset 0x20). If you are changing the EPC length, you need to write the PC word as well (offset 1).
2009-07-24 17:38:43 UTC in LLRP toolkit
-
Gen2 specifies a TID field that is required. It contains a maskID which identifies the manufacturer of the tag silicon, as well as a model number, which is vendor specific, but signifies what model of silicon is produced. Gen2 does not require a unique TID that is different on each chip, but has optional serialized TID information in the new standard. (6.3.2.1.3 in the new standard)
TID mem.
2009-01-14 19:27:56 UTC in LLRP toolkit
-
Numerous bugs were fixed in LTK.NET. A PacketTest directory was added that runs the dx101 tests through the library (round trip) and validates that packets match.
2009-01-13 20:36:34 UTC in LLRP toolkit
