Scott Nixon

Hah, wouldn't be the first time the simulator happily digests code that isn't LRM compatible :) No worries, I can clean up my code to match the LRM if that is what it specifies.

cp_read_write : coverpoint trans.kind iff !(a == 1'b) { type_option.comment = "Read/Write"; bins cp_read = {READ}; bins cp_write = {WRITE}; }

Specify blocks don't parse correctly for min:typ:max timing data

Dozens, if not 100's. Typically see VHDL in about 70-80% of the projects I work on. Certainly would be useful, but more so for designers as I rarely have to dig down that far just doing verfication...

They were in "problems". I deleted them and did a "Project->Clean" and they are gone! Thanks!!!

Unary Logic Negation Operator not parsed correctly

I removed the VHDL files from my ".F" file, but they still show up in the error log. I did a "Clean Project" and "SV Index rebuild" but neither eliminated them. Do I need to start over with a fresh project?

That was my mistake, thanks!