IOAPIC in BOCHS - WinXP 64 in MP version

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As you said IOAPIC needs some work and it is not actually
works. Bochs successfully boot several Linux SMP images
with noapic option (which means without I/O APIC) and fails
to boot full SMP kernel ;(

The problem that nobody of currently active Bochs developers
understand this area enough to recognize what is the problem
with I/O APIC and how to fix it. May be you can help here ...

Thanks,
Stanislav

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Stanislav,

Is there any dccumentation on the current implementation of
the PIC or Local APICs in the CPU model?
I'd be glad to implement the IOAPIC model into Bochs. But I
may need some help understanding whats already there. If you
can send any documentation etc my way, I'd really appreciate it.

Sailor

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I don't know to explain which of I/O APIC features is not
implemented (otherwise I could just got seat with docs and
implement them by myself). I learned APIC and I/O APIC
code and think that all neccessary functionality is already in.
Might be there are some bugs which caused to the
implementation PANIC but I don't know.
The APIC code is in cpu/apic.cc
The I/O APIC code is in iodev/ioapic.cc
The PIC code is in pic.cc
I think I already understand what's going on in the APIC and
I/O APIC modules so you could feel free asking questions.

Thanks,
Stanislav

P.S> Please post some contact information like e-mail ...

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Hi Stanislav,

Thanks for the info.

Sorry for taking so long to get back but I wanted to have
something substantial before I posted something.

Actually I've been going through the Bochs LAPIC code and
the IOAPIC code.
Actually everything is there in the IOAPIC and there aren't
any holes in the implementation either. I'm going through
the LAPIC code and it also appears mostly implemented but
I'm still verifying a few things.

As for why Win2K3 server x64 version fails with a "enable
Local APIC ....." - I'm not sure why. I spent a whole day
tracing the code and it initially seemed like setup was
giving this error after doing a cpuid instruction. I've
verified that the cpuid is returning the correct
information, including that APIC is enabled. Nothing shows
up in the logs as to why it thinks APIC is not enabled - no
failed writes to registers etc. I've also consulted the
Opteron programming manuals to make sure that the values
returned by Bochs are correct and so far I can't find
anything wrong.

As for why Win2k3 server x32, before I would be getting a
LAPIC panic message and then setup would crash. I recompiled
Bochs, without optimization (because I wanted to single step
through it). Now I still get the LAPIC panic messages but it
seems to be stuck at "Setup is Starting Windows" stage. Not
sure why.

So far it seems that there is nothing in the implementation
of the APIC itself that might be causing the problem -
however there are too many other things happening that I
don't understand. I'm still debugging the problem but I have
to have more documentation on the general architecture of
Bochs - reading the code and trying to understand just takes
too long.

Btw, you can contact me at adnan(at)khaleel(dot)us

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One of the known problems is timers, in particular TSC timer.
Currently Bochs doesn't support writing to TSC_MSR and
Linux used it for calibrating CPU speed.
There is two different TSC patches in Bochs patches folder,
with applying of one of these patches it continue little bit
more in Linux SMP boot.
Stanislav

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Also we still have tons of
---> 00016562656p[IOAP ] >>PANIC<< deliver failed for
vector f8: no APICs in destination bitmask
PANIC messages when booting with I/O APIC enabled, it
looks like servicing of I/O interrupts by APIC is not modelled
correctly. I could not say nothing about that is wrong but the
PANICs are here ;(

Thanks,
Stanislav

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Hi Stanislav,

I downloaded the the prerelease3 files and I tried running
Win2k3 server 32bit on it and I no longer get an APIC
panics. However setup does not go beyond "Setup is Starting
Windows" .. seems stuck in an endless loop or something.

Still working on this.

Sailor

Anyways here is the bochsout.txt

00000000000i[ ] Bochs x86 Emulator 2.2.pre3
00000000000i[ ] Build from CVS snapshot on April 16, 2005
00000000000i[ ] System configuration
00000000000i[ ] processors: 4
00000000000i[ ] A20 line support: yes
00000000000i[ ] APIC support: yes
00000000000i[ ] CPU configuration
00000000000i[ ] level: 6
00000000000i[ ] fpu support: yes
00000000000i[ ] paging support: yes, tlb enabled: yes
00000000000i[ ] mmx support: yes
00000000000i[ ] sse support: 2
00000000000i[ ] v8086 mode support: yes
00000000000i[ ] 3dnow! support: yes
00000000000i[ ] PAE support: yes
00000000000i[ ] PGE support: yes
00000000000i[ ] PSE support: yes
00000000000i[ ] x86-64 support: yes
00000000000i[ ] SEP support: no
00000000000i[ ] Optimization configuration
00000000000i[ ] Guest2HostTLB support: no
00000000000i[ ] RepeatSpeedups support: yes
00000000000i[ ] Icache support: no
00000000000i[ ] Host Asm support: yes
00000000000i[ ] Fast function calls: no
00000000000i[MEM0 ] allocated memory at 0x40467008. after
alignment, vector=0x40468000
00000000000i[MEM0 ] 1024.00MB
00000000000i[MEM0 ] rom at 0xf0000/65536
('/home/adnan.khaleel/tmp/Bochs/share/bochs/BIOS-bochs-4-processors')
00000000000i[MEM0 ] rom at 0xc0000/32768
('/home/adnan.khaleel/tmp/Bochs/share/bochs/VGABIOS-lgpl-latest')
00000000000i[APIC?] local apic in initializing
00000000000i[APIC?] local apic in initializing
00000000000i[APIC0] 80686
00000000000i[APIC0] local apic in CPU apicid=00 initializing
00000000000i[CPU0 ] CPU[0] is an application processor.
Halting until IPI.
00000000000i[APIC?] local apic in initializing
00000000000i[APIC?] local apic in initializing
00000000000i[APIC1] 80686
00000000000i[APIC1] local apic in CPU apicid=01 initializing
00000000000i[CPU1 ] CPU[1] is an application processor.
Halting until IPI.
00000000000i[APIC?] local apic in initializing
00000000000i[APIC?] local apic in initializing
00000000000i[APIC2] 80686
00000000000i[APIC2] local apic in CPU apicid=02 initializing
00000000000i[CPU2 ] CPU[2] is the bootstrap processor
00000000000i[APIC?] local apic in initializing
00000000000i[APIC?] local apic in initializing
00000000000i[APIC3] 80686
00000000000i[APIC3] local apic in CPU apicid=03 initializing
00000000000i[CPU3 ] CPU[3] is an application processor.
Halting until IPI.
00000000000i[CMOS ] Using local time for initial clock
00000000000i[CMOS ] Setting initial clock to: Tue Apr 19
14:37:51 2005 (time0=1113939471)
00000000000i[DMA ] channel 4 used by cascade
00000000000i[DMA ] channel 2 used by Floppy Drive
00000000000i[FDD ] tried to open '/dev/fd0' read/write:
Permission denied
00000000000i[FDD ] tried to open '/dev/fd0' read only:
Permission denied
00000000000i[FDD ] fd0: '/dev/fd0' ro=1, h=0,t=0,spt=0
00000000000i[FDD ] tried to open 'b.img' read/write: No
such file or directory
00000000000i[FDD ] tried to open 'b.img' read only: No such
file or directory
00000000000i[FDD ] fd1: 'b.img' ro=1, h=0,t=0,spt=0
00000000000i[XGUI ] test_alloc_colors: 16 colors available
out of 16 colors tried
00000000000i[XGUI ] font 8 wide x 16 high, display depth = 24
00000000000i[VGA ] interval=300000
00000000000i[VGA ] VBE Bochs Display Extension Enabled
00000000000i[ ] init_mem of 'harddrv' plugin device by
virtual method
00000000000i[ ] init_mem of 'keyboard' plugin device by
virtual method
00000000000i[ ] init_mem of 'serial' plugin device by
virtual method
00000000000i[ ] init_mem of 'parallel' plugin device by
virtual method
00000000000i[ ] init_mem of 'extfpuirq' plugin device by
virtual method
00000000000i[ ] init_mem of 'speaker' plugin device by
virtual method
00000000000i[ ] init_dev of 'harddrv' plugin device by
virtual method
00000000000i[HD ] HD on ata0-0:
'/home/dveng/Adnan/QEMU_Bochs/hdd.img' 'flat' mode
00000000000i[HD ] CD on ata0-1:
'/home/dveng/Adnan/OSImages/win2k3entserver.iso'
00000000000i[CD ] load cdrom with
path=/home/dveng/Adnan/OSImages/win2k3entserver.iso
00000000000i[CD ] Opening image file
/home/dveng/Adnan/OSImages/win2k3entserver.iso as a cd.
00000000000i[HD ] Media present in CD-ROM drive
00000000000i[CD ] cdrom size is 572514304 bytes
00000000000i[HD ] translation on ata0-0 set to 'none'
00000000000i[HD ] Using boot sequence cdrom, disk, none
00000000000i[HD ] Floppy boot signature check is enabled
00000000000i[ ] init_dev of 'keyboard' plugin device by
virtual method
00000000000i[KBD ] will paste characters every 1000
keyboard ticks
00000000000i[ ] init_dev of 'serial' plugin device by
virtual method
00000000000i[SER ] com1 at 0x03f8 irq 4
00000000000i[ ] init_dev of 'parallel' plugin device by
virtual method
00000000000i[PAR ] parallel port 1 at 0x0378 irq 7
00000000000i[ ] init_dev of 'extfpuirq' plugin device by
virtual method
00000000000i[ ] init_dev of 'speaker' plugin device by
virtual method
00000000000i[SPEAK] Failed to open /dev/console: Success
00000000000i[SPEAK] Deactivating beep on console
00000000000i[ ] reset of 'harddrv' plugin device by
virtual method
00000000000i[ ] reset of 'keyboard' plugin device by
virtual method
00000000000i[ ] reset of 'serial' plugin device by
virtual method
00000000000i[ ] reset of 'parallel' plugin device by
virtual method
00000000000i[ ] reset of 'extfpuirq' plugin device by
virtual method
00000000000i[ ] reset of 'speaker' plugin device by
virtual method
00000000000i[ ] set SIGINT handler to bx_debug_ctrlc_handler
00000004150i[BIOS ] rombios.c,v 1.131 2005/04/06 18:01:14
vruppert Exp $
00000325050i[KBD ] reset-disable command received
00000431750i[VBIOS] VGABios $Id: vgabios.c,v 1.59 2004/07/18
20:22:43 vruppert Exp $
00000431825i[VGA ] VBE known Display Interface b0c0
00000431850i[VGA ] VBE known Display Interface b0c3
00000434775i[VBIOS] VBE Bios $Id: vbe.c,v 1.45 2004/07/22
18:37:29 vruppert Exp $
00000712050i[BIOS ] ata0-0: PCHS=615/6/17 translation=none
LCHS=615/6/17
00003000000i[XGUI ] charmap update. Font Height is 16
00009000000i[XGUI ] charmap update. Font Height is 16
00011112675i[BIOS ] PCI BIOS: PCI not present
00011308450i[BIOS ] int13_harddisk: function 15, unmapped
device for ELDL=81
00099213125i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00099214925i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00099216750i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00099218550i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101953000i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101954825i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101956625i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101958450i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101970900i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101972775i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101974650i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00101976550i[FDD ] attempt to read/write sector 1,
sectors/track=0 with media not present
00196315725i[APIC2] warning: misaligned or wrong-size APIC
access. addr=fee00030 len=1
00823651825i[APIC2] warning: misaligned or wrong-size APIC
access. addr=fee00030 len=1
00823652075i[IOAP ] IOAPIC: could not write, IOREGSEL=0x01
00823652075i[IOAP ] IOAPIC: could not write, IOREGSEL=0x01
00823652250i[APIC2] Broadcast IPI for vector 0 delivery_mode 0x5
00823652250i[APIC2] INIT with Level&Deassert: synchronize
arbitration IDs
00823673225i[IOAP ] IOAPIC: setting id to 0x4
00933898975i[CPU2 ] MOV_RdCd: read of CR4
00933979525i[CPU2 ] MOV_RdCd: read of CR4
00934061425i[CPU2 ] MOV_RdCd: read of CR4
00934420975i[CPU2 ] MOV_RdCd: read of CR4
00934499600i[CPU2 ] MOV_RdCd: read of CR4
00934612600i[CPU2 ] MOV_RdCd: read of CR4
00934827700i[CPU2 ] MOV_RdCd: read of CR4
00934907825i[CPU2 ] MOV_RdCd: read of CR4
00935007625i[CPU2 ] MOV_RdCd: read of CR4
00935089800i[CPU2 ] MOV_RdCd: read of CR4
00935167350i[CPU2 ] MOV_RdCd: read of CR4
00935264800i[CPU2 ] MOV_RdCd: read of CR4
00935363325i[CPU2 ] MOV_RdCd: read of CR4
00935515850i[CPU2 ] MOV_RdCd: read of CR4
00935591800i[CPU2 ] MOV_RdCd: read of CR4
00935683175i[CPU2 ] MOV_RdCd: read of CR4
00935759100i[CPU2 ] MOV_RdCd: read of CR4
00935835050i[CPU2 ] MOV_RdCd: read of CR4
00935912400i[CPU2 ] MOV_RdCd: read of CR4
00935988975i[CPU2 ] MOV_RdCd: read of CR4
00936065350i[CPU2 ] MOV_RdCd: read of CR4
00936165225i[CPU2 ] MOV_RdCd: read of CR4
00936322400i[CPU2 ] MOV_RdCd: read of CR4
00936415075i[CPU2 ] MOV_RdCd: read of CR4
00936561400i[CPU2 ] MOV_RdCd: read of CR4
00936649625i[CPU2 ] MOV_RdCd: read of CR4
00936726975i[CPU2 ] MOV_RdCd: read of CR4
00936891125i[CPU2 ] MOV_RdCd: read of CR4
00936988775i[CPU2 ] MOV_RdCd: read of CR4
00937067250i[CPU2 ] MOV_RdCd: read of CR4
00937221000i[CPU2 ] MOV_RdCd: read of CR4
00937300100i[CPU2 ] MOV_RdCd: read of CR4
00937377575i[CPU2 ] MOV_RdCd: read of CR4
00937487750i[CPU2 ] MOV_RdCd: read of CR4
00937557475i[CPU2 ] MOV_RdCd: read of CR4
00937640550i[CPU2 ] MOV_RdCd: read of CR4
00937721025i[CPU2 ] MOV_RdCd: read of CR4
00937796125i[CPU2 ] MOV_RdCd: read of CR4
00937893000i[CPU2 ] MOV_RdCd: read of CR4
00938002525i[CPU2 ] MOV_RdCd: read of CR4
00938078125i[CPU2 ] MOV_RdCd: read of CR4
00938157400i[CPU2 ] MOV_RdCd: read of CR4
00938228925i[CPU2 ] MOV_RdCd: read of CR4
00938308150i[CPU2 ] MOV_RdCd: read of CR4
00938379775i[CPU2 ] MOV_RdCd: read of CR4
00938498800i[CPU2 ] MOV_RdCd: read of CR4
00938602550i[CPU2 ] MOV_RdCd: read of CR4
00938676725i[CPU2 ] MOV_RdCd: read of CR4
00938758225i[CPU2 ] MOV_RdCd: read of CR4
00938896400i[CPU2 ] MOV_RdCd: read of CR4
00938968300i[CPU2 ] MOV_RdCd: read of CR4
00939092800i[CPU2 ] MOV_RdCd: read of CR4
00939167150i[CPU2 ] MOV_RdCd: read of CR4
00939249775i[CPU2 ] MOV_RdCd: read of CR4
00939323850i[CPU2 ] MOV_RdCd: read of CR4
00939431575i[CPU2 ] MOV_RdCd: read of CR4
00939528950i[CPU2 ] MOV_RdCd: read of CR4
00939601975i[CPU2 ] MOV_RdCd: read of CR4
00939679475i[CPU2 ] MOV_RdCd: read of CR4
00939783550i[CPU2 ] MOV_RdCd: read of CR4
00939899100i[CPU2 ] MOV_RdCd: read of CR4
00940023500i[CPU2 ] MOV_RdCd: read of CR4
00940150600i[CPU2 ] MOV_RdCd: read of CR4
00940224400i[CPU2 ] MOV_RdCd: read of CR4
00940320400i[CPU2 ] MOV_RdCd: read of CR4
00940400475i[CPU2 ] MOV_RdCd: read of CR4
00940482050i[CPU2 ] MOV_RdCd: read of CR4
00940561200i[CPU2 ] MOV_RdCd: read of CR4
00940640000i[CPU2 ] MOV_RdCd: read of CR4
00940714375i[CPU2 ] MOV_RdCd: read of CR4
00940787250i[CPU2 ] MOV_RdCd: read of CR4
00940860775i[CPU2 ] MOV_RdCd: read of CR4
00940930075i[CPU2 ] MOV_RdCd: read of CR4
00941010350i[CPU2 ] MOV_RdCd: read of CR4
00941117800i[CPU2 ] MOV_RdCd: read of CR4
00941218075i[CPU2 ] MOV_RdCd: read of CR4
00941298625i[CPU2 ] MOV_RdCd: read of CR4
00941378725i[CPU2 ] MOV_RdCd: read of CR4
00941461600i[CPU2 ] MOV_RdCd: read of CR4
00941542675i[CPU2 ] MOV_RdCd: read of CR4
00941613875i[CPU2 ] MOV_RdCd: read of CR4
00941684950i[CPU2 ] MOV_RdCd: read of CR4
00941759500i[CPU2 ] MOV_RdCd: read of CR4
00941832575i[CPU2 ] MOV_RdCd: read of CR4
00941902525i[CPU2 ] MOV_RdCd: read of CR4
00942039950i[CPU2 ] MOV_RdCd: read of CR4
00942115325i[CPU2 ] MOV_RdCd: read of CR4
00942200525i[CPU2 ] MOV_RdCd: read of CR4
00942272425i[CPU2 ] MOV_RdCd: read of CR4
00942440200i[CPU2 ] MOV_RdCd: read of CR4
00942822850i[CPU2 ] MOV_RdCd: read of CR4
00942899950i[CPU2 ] MOV_RdCd: read of CR4
00943011300i[CPU2 ] MOV_RdCd: read of CR4
00943112975i[CPU2 ] MOV_RdCd: read of CR4
00943201525i[CPU2 ] MOV_RdCd: read of CR4
00943272950i[CPU2 ] MOV_RdCd: read of CR4
00943350675i[CPU2 ] MOV_RdCd: read of CR4
00943495275i[CPU2 ] MOV_RdCd: read of CR4
00943670875i[CPU2 ] MOV_RdCd: read of CR4
00944085775i[CPU2 ] MOV_RdCd: read of CR4
00946100325i[CPU2 ] WBINVD: (ignoring)
21474836450e[APIC0] CPU apicid=00: bx_local_apic_c::periodic
called, timer_active==0

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This is exactly the same picture as I get when trying to boot
WinNT SMP. I have no idea what is the endless loop that
CPU executes and why it cannot leave it.
Thee people say that moderm OSes like WinXP require ACPI
to boot SMP. I also waiting for somebody who could explain
me why ACPI (AFAIR it is power control interface) required for
SMP boot.

Thanks,
Stanislav

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You know that might be true about the ACPI. Let me check
around on that a little bit.

Sailor

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user_id=1263217

Hi Stanislav,

I've done quite a bit of searching and reading on the ACPI
spec 2.0/3.0 and also MicroSoft documents.
Well it does appear that ACPI replaces the Multiprocessor
Spec 1.4 which initially described APIC implementations. I
still don't completely understand how the interrupt schemes
differ in MP 1.4 and ACPI 2.0 but I'm thinking for the most
part they should be very similar with a few differences.
I'll continue studying these documents to see whats the
difference and also what changes would be necessary in Bochs
to implement this.

It seems that to implement the above may represent quite a
bit of additional work on Bochs, especially if we have to
represent the different processor states the ACPI requires.
In view of this, I want to concentrate on why Bochs never
goes beyond "Setup is starting Windows" in Win2k3 32bit as I
think this problem has to have a more straight forward
solution. Would you have any idea how I could go about
debugging that? The problem is I need a diassembler output
for more than what bochs has executed so I can see where in
the loops Bochs is getting stuck. Ideally I would need to
compare this with a case where (maybe from a uniprocessor
case) it goes beyond this point - even this is not trivial
but its doable. Do you have any suggestions on what might be
easier?

Sailor

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I fixed several small APIC problems, in particilar
highest_priority_int calculation in isr or irr and this is changed
the behaviour of WinNT4 SMP I am trying to boot ...
The simulation reached the boot screen and detected 2
CPUs, successfully started them and when stalled in some
infitite loop ...

Now this is what it does in the loop:

00430108553i[CPU0 ] MOV_RdCd: read of CR4
00546719093d[APIC0] CPU apicid=00: comparing MDA 01 to
my LDR 01 -> Match
00546719093d[APIC1] CPU apicid=01: comparing MDA 01 to
my LDR 02 -> Not a match
00546719093d[APIC0] set arbitration ID to 0
00546719093d[APIC1] set arbitration ID to 2
00546719093d[APIC0] Local apic on CPU apicid=00: trigger
interrupt vector=0xd1
00546719093d[APIC0] service_local_apic(): setting INTR=1
for vector 0xd1
00546719093d[APIC0] CPU apicid=00: acknowledge_int
returning vector 0xd1
00546719123d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00546719123d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546719188d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 00040041
00546719188d[APIC0] CPU apicid=00: write 0x000c00d1 to
APIC address fee00300
00546719188d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00546719188d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00546719188d[APIC0] set arbitration ID to 1
00546719188d[APIC1] set arbitration ID to 0
00546719188d[APIC1] Local apic on CPU apicid=01: trigger
interrupt vector=0xd1
00546719188d[APIC1] service_local_apic(): setting INTR=1
for vector 0xd1
00546719188d[APIC1] CPU apicid=01: acknowledge_int
returning vector 0xd1
00546719223d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00546719223d[APIC1] CPU apicid=01: write 0x000000d1 to
APIC address fee00080
00546719278d[APIC0] CPU apicid=00: write 0x00000000 to
APIC address fee000b0
00546719278d[APIC0] CPU apicid=00: Wrote 0x0 to EOI
00546719278d[APIC0] CPU apicid=00: local apic received
EOI, hopefully for vector 0xd1
00546719278d[APIC1] CPU apicid=01: write 0x00000000 to
APIC address fee000b0
00546719278d[APIC1] CPU apicid=01: Wrote 0x0 to EOI
00546719278d[APIC1] CPU apicid=01: local apic received
EOI, hopefully for vector 0xd1
00546719283d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546719283d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00546719283d[APIC1] CPU apicid=01: write 0x00000041 to
APIC address fee00080
00546719283d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00546875343d[APIC0] CPU apicid=00: comparing MDA 01 to
my LDR 01 -> Match
00546875343d[APIC1] CPU apicid=01: comparing MDA 01 to
my LDR 02 -> Not a match
00546875343d[APIC0] set arbitration ID to 0
00546875343d[APIC1] set arbitration ID to 1
00546875343d[APIC0] Local apic on CPU apicid=00: trigger
interrupt vector=0xd1
00546875343d[APIC0] service_local_apic(): setting INTR=1
for vector 0xd1
00546875343d[APIC0] CPU apicid=00: acknowledge_int
returning vector 0xd1
00546875373d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00546875373d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546875438d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 000c00d1
00546875438d[APIC0] CPU apicid=00: write 0x000c00d1 to
APIC address fee00300
00546875438d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00546875438d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00546875438d[APIC0] set arbitration ID to 1
00546875438d[APIC1] set arbitration ID to 0
00546875438d[APIC1] Local apic on CPU apicid=01: trigger
interrupt vector=0xd1
00546875438d[APIC1] service_local_apic(): setting INTR=1
for vector 0xd1
00546875438d[APIC1] CPU apicid=01: acknowledge_int
returning vector 0xd1
00546875468d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00546875468d[APIC1] CPU apicid=01: write 0x000000d1 to
APIC address fee00080
00546875523d[APIC1] CPU apicid=01: write 0x00000000 to
APIC address fee000b0
00546875523d[APIC1] CPU apicid=01: Wrote 0x0 to EOI
00546875523d[APIC1] CPU apicid=01: local apic received
EOI, hopefully for vector 0xd1
00546875528d[APIC1] CPU apicid=01: write 0x00000041 to
APIC address fee00080
00546875528d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00546875538d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 000c00d1
00546875538d[APIC0] CPU apicid=00: write 0x00040041 to
APIC address fee00300
00546875538d[APIC0] local::get_delivery_bitmask returning
0x0001 shorthand=0x1
00546875538d[APIC0] local::get_delivery_bitmask returning
0x0001 shorthand=0x1
00546875538d[APIC0] set arbitration ID to 0
00546875538d[APIC1] set arbitration ID to 1
00546875538d[APIC0] Local apic on CPU apicid=00: trigger
interrupt vector=0x41
00546875538d[APIC0] service_local_apic(): setting INTR=1
for vector 0x41
00546875538d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 00040041
00546875543d[APIC0] CPU apicid=00: acknowledge_int
returning vector 0x41
00546875568d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00546875568d[APIC0] CPU apicid=00: write 0x00000041 to
APIC address fee00080
00546875568d[APIC0] CPU apicid=00: write 0x00000000 to
APIC address fee000b0
00546875568d[APIC0] CPU apicid=00: Wrote 0x0 to EOI
00546875568d[APIC0] CPU apicid=00: local apic received
EOI, hopefully for vector 0xd1
00546875588d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 00000041
00546875598d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546875678d[APIC0] CPU apicid=00: write 0x00000041 to
APIC address fee00080
00546875678d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 00000041
00546875693d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546875693d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00546875728d[APIC0] CPU apicid=00: write 0x00000000 to
APIC address fee000b0
00546875728d[APIC0] CPU apicid=00: Wrote 0x0 to EOI
00546875728d[APIC0] CPU apicid=00: local apic received
EOI, hopefully for vector 0x41
00546875733d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00546875733d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00547031593d[APIC0] CPU apicid=00: comparing MDA 01 to
my LDR 01 -> Match
00547031593d[APIC1] CPU apicid=01: comparing MDA 01 to
my LDR 02 -> Not a match
00547031593d[APIC0] set arbitration ID to 0
00547031593d[APIC1] set arbitration ID to 2
00547031593d[APIC0] Local apic on CPU apicid=00: trigger
interrupt vector=0xd1
00547031593d[APIC0] service_local_apic(): setting INTR=1
for vector 0xd1
00547031593d[APIC0] CPU apicid=00: acknowledge_int
returning vector 0xd1
00547031623d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00547031623d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00547031688d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 00040041
00547031688d[APIC0] CPU apicid=00: write 0x000c00d1 to
APIC address fee00300
00547031688d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00547031688d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00547031688d[APIC0] set arbitration ID to 1
00547031688d[APIC1] set arbitration ID to 0
00547031688d[APIC1] Local apic on CPU apicid=01: trigger
interrupt vector=0xd1
00547031688d[APIC1] service_local_apic(): setting INTR=1
for vector 0xd1
00547031693d[APIC1] CPU apicid=01: acknowledge_int
returning vector 0xd1
00547031723d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00547031728d[APIC1] CPU apicid=01: write 0x000000d1 to
APIC address fee00080
00547031778d[APIC0] CPU apicid=00: write 0x00000000 to
APIC address fee000b0
00547031778d[APIC0] CPU apicid=00: Wrote 0x0 to EOI
00547031778d[APIC0] CPU apicid=00: local apic received
EOI, hopefully for vector 0xd1
00547031783d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00547031783d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00547031783d[APIC1] CPU apicid=01: write 0x00000000 to
APIC address fee000b0
00547031783d[APIC1] CPU apicid=01: Wrote 0x0 to EOI
00547031783d[APIC1] CPU apicid=01: local apic received
EOI, hopefully for vector 0xd1
00547031783d[APIC1] CPU apicid=01: write 0x00000041 to
APIC address fee00080
00547031788d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00547187843d[APIC0] CPU apicid=00: comparing MDA 01 to
my LDR 01 -> Match
00547187843d[APIC1] CPU apicid=01: comparing MDA 01 to
my LDR 02 -> Not a match
00547187843d[APIC0] set arbitration ID to 0
00547187843d[APIC1] set arbitration ID to 1
00547187843d[APIC0] Local apic on CPU apicid=00: trigger
interrupt vector=0xd1
00547187843d[APIC0] service_local_apic(): setting INTR=1
for vector 0xd1
00547187843d[APIC0] CPU apicid=00: acknowledge_int
returning vector 0xd1
00547187873d[APIC0] CPU apicid=00: read from APIC
address fee00080 = 000000d1
00547187873d[APIC0] CPU apicid=00: write 0x000000d1 to
APIC address fee00080
00547187938d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 000c00d1
00547187938d[APIC0] CPU apicid=00: write 0x000c00d1 to
APIC address fee00300
00547187938d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00547187938d[APIC0] local::get_delivery_bitmask returning
0x0002 shorthand=0x3
00547187938d[APIC0] set arbitration ID to 1
00547187938d[APIC1] set arbitration ID to 0
00547187938d[APIC1] Local apic on CPU apicid=01: trigger
interrupt vector=0xd1
00547187938d[APIC1] service_local_apic(): setting INTR=1
for vector 0xd1
00547187938d[APIC1] CPU apicid=01: acknowledge_int
returning vector 0xd1
00547187973d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00547187973d[APIC1] CPU apicid=01: write 0x000000d1 to
APIC address fee00080
00547188028d[APIC1] CPU apicid=01: write 0x00000000 to
APIC address fee000b0
00547188028d[APIC1] CPU apicid=01: Wrote 0x0 to EOI
00547188028d[APIC1] CPU apicid=01: local apic received
EOI, hopefully for vector 0xd1
00547188033d[APIC1] CPU apicid=01: write 0x00000041 to
APIC address fee00080
00547188033d[APIC1] CPU apicid=01: read from APIC
address fee00080 = 00000041
00547188038d[APIC0] CPU apicid=00: read from APIC
address fee00300 = 000c00d1
00547188038d[APIC0] CPU apicid=00: write 0x00040041 to
APIC address fee00300
00547188038d[APIC0] local::get_delivery_bitmask returning
0x0001 shorthand=0x1
00547188038d[APIC0] local::get_delivery_bitmask returning
0x0001 shorthand=0x1
00547188038d[APIC0] set arbitration ID to 0
...

I think there is some chance that Bochs has some bugs in
lowest priority interrupt handling and interrupts acknowledge
but I still not understand APIC enough to do something in this
area. But am learning fast so hopefully before final 2.2 release
I'll advance little more ...

Thanks,
Stanislav

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For winxp 64, I am able to get into "windows setup" blue
screen, with the following two patches:

1) Alex Beregszaszi's "early ACPI support in BIOS" patch
2) my own patch that creates a MP table for single processor
configuration in bios/rombios.c

It turns out Windows 64 needs to see both MP table and the
ACPI table in order to use APIC.

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chengyuqing
could u please share ur bios? ;)

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Hi,

On 2005-04-27 11:39 Stanislav wrote:

I think there is some chance that Bochs has some bugs in
lowest priority interrupt handling and interrupts acknowledge
but I still not understand APIC enough to do something in
this
area. But am learning fast so hopefully before final 2.2
release
I'll advance little more ...

IMHO Bochs definately has bugs with lowest priority
interrupt handling - my tests show that instead of the
interrupt being sent to the lowest priority CPU it's
actually sent to all CPUs.

On 2005-04-20 10:28 Stanislav wrote:

Thee people say that moderm OSes like WinXP require ACPI
to boot SMP. I also waiting for somebody who could explain
me why ACPI (AFAIR it is power control interface) required
for
SMP boot.

Have you heard the old joke - "a camel is a horse designed
by a committee"? ACPI was designed by a committee and
largely influenced by Microsoft - it's a camel with 12
humps, a few udders and horns at both ends.

The "Advanced Configuration and Power Interface
Specification" (ACPI) covers power management and
configuration (and is intended to be portable to other
architectures).

There are 2 main parts to ACPI. The first part is an
interpretted OOP language (called ACPI machine language or
AML - generated from ACPI Source Code or ASL) that's used by
"firmware" (ROMs, etc) to provide power management and
configuration services to the operating system.

The second part is a collection of tables that the OS uses
for configuration before the AML interpretter is ready to
run (ie. during boot). These ACPI tables include a full
replacement for the MP specification (IO APICs, local
APICs/CPUs, IRQs) and a pile of other stuff - the SRAT table
(used to define NUMA memory domains, etc), system
information (if ISA is supported, if the computer is
"headless", RTC/CMOS addresses for time/date/century
information, what to write to which IO port for "soft power
off", etc).

To complicate things more, the new version of the
specification (ACPI 3.0) seems to include full device lists,
much like the PCI configuration space, ISA Plug & Play and
extra devices (PC/AT motherboard hardware) rolled into one.
ACPI also uses SMI/SMM behind the scenes, and incorporates
other standards like SMBus and EFI.

IMHO it would be easy for someone to come to the conclusion
that ACPI is Microsofts attempt at making life extremely
difficult for their competition (for e.g. AFAIK the Linux
ACPI initiative is still struggling with the basics, despite
heavy support from Intel developers).

What does all this mean for Bochs? Well, if bochs supported
the ACPI tables only, then OSs like Windows and Linux would
expect the full AML OOP stuff (ie. you'd need both). The
complexity of ACPI could double the size of the Bochs
project, and triple the headaches - a major problem
considering that almost all programmers have very little
experience with ACPI (if any).

Another problem would be the maximum size of a BIOS image -
the current 64 KB ROM would be too small for all this, and
you'd need to consider starting the CPU at 0xFFFFFFF0 (CS
base = 0xFFFF0000 like a real CPU) and then remapping part
of it into it's normal place below 0x00100000. Then there's
deciding how (or if?) to emulate SMM/SMI and SMBus (and
finding out WTF SMI/SMM is actually being used for, in
additional to ACPI/APM and making USB keyboards & mice look
like legacy PS/2 devices).

As you can see, IMHO ACPI support would be a huge
undertaking. The unfortunate problem is that all future
Microsoft OSs will require it, and other OSs like Linux
haven't got much choice but to support it. This means (for
Bochs) ACPI support will become increasingly unavoidable
with time.

Cheers,

Brendan - btrotter AT gmail.com

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Sorry for not answering too much time, I just didn't seen it
was updated ;(
From our last talk Bochs moved through several important
stages:
1. The CPU starting execution at 0xFFFFFFF0 (CS
base = 0xFFFF0000 like a real CPU)
2. The maximum BIOS size increased up to 512K
3. Several bugs in APIC code were fixed, but unfortunatelly
still there are other bugs ;(
4. I plan to release a patch which writes acpi.bin ROM
images with ACPI MP tables for 2,4 or 8 CPUs. This ROm
could be loaded as optromimage at address 0xe0000 at
tested.

I ask you to look on the ACPI tables and check if they
working correctly. I tried to start Win64 installation with this
acpi.bin and it passed APIC check which failed before but
installation freezes on message "Starting windows setup ...".
When killing simulation it could be seen that Bochs just
executing PAUSE (REP NOP) instruction.

Also when trying to boot WinXP SMP configuration it fails on
some stupid PANIC, looks like it going to execute bogus
memory ...

I don't know if any of APIC problem were successfully fixed,
at least we had several commits to APIC code which really
fixed some bugs. I invite you to help checking if these fixes
helpe somewhere and if so what is the current picture.

Thanks,
Stanislav

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If somebody want to try, I uploaded to this bug report ACPI
images (BIN) together with C-program which generated them.

Stanislav

single cpu ACPI MP tables

ACPI MP tables for 2 CPU configuration

ACPI MP tables for 4 CPU configuration

ACPI MP tables for 8 CPU configuration

ACPI.bin generator

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Hi Stanislav,

Finally got some time from work. I downloaded the new
version of Bochs 2.2.6 just to see what the current status
is. I still can't get much further with the Windows 2k3,
same IOAPIC problem. I guess the dynamic SRAT tables are
still not implemented and/or merged into the trunk. I read
in the change log that WinNT MP now boots, is this correct?
Also what is the status of Brendan who offered to rewrite
the entire BIOS and ACPI portion?

I have some free time now that I can do some more work on
this so please let me know if there is anything in specific
that you would like me to look at.

Sincerely

Sailor

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APIC issue is already fixed and even some ACPI support presents in CVS.
This bug report could be closed, you are welcome to try again and open a new more recent one.

Thanks,
Stanislav