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Hi,
I've used in the past a PCMCIA to parallel converter that creates a "true" LPT port. With it I can configure fpgas using impact without problems. You must set the cable just like the normal parallel cable. I think your cable should work in the same way. Maybe you need to change the LPT port.
You tried using urjtag with this cable? You can set the cable like the normal parallel cable...
2010-01-05 14:35:08 UTC by gasrodriguez
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Hello,
I want to implement some designs on FPGA. I have acquired the ISE 9.1 software as well as spartan-2 based board , namely Digilent board II2 ( http://www.digilentinc.com/Data/Products/D2E/D2E-rm.PDF ) As you see in the PDF file (page 2 onwards), the board is configured via an ordinary parallel DB-25 pin ports. Unfortunately my PC does not have a parallel port. As such, i bought a usb to...
2010-01-05 00:06:51 UTC by ang777us
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Hi,
As far as I can see, this patch adds jtag definition files for the mentioned devices. Do the BSDL files delivered by Xilinx work as well? If yes, I'd like to avoid adding more package-specific jtag files to the database.
Best regards
Arnim.
2009-12-30 00:23:30 UTC by arniml
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The jedec.c file changed a lot with respect to detection of x8/x16 flash chips. I was therefore not able to apply your patch directly to SVN trunk. Instead, I copied the new flash definitions but avoided to change the macro definitions.
Please feel free to reopen this issue in case something is broken or missing.
Partly applied to SVN r1688.
2009-12-30 00:19:28 UTC by arniml
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arniml committed revision 1688 to the Universal JTAG library, server and tools SVN repository, changing 2 files.
2009-12-30 00:16:53 UTC by arniml
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Applied as SVN r1687, thanks!
2009-12-29 23:53:35 UTC by arniml
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arniml committed revision 1687 to the Universal JTAG library, server and tools SVN repository, changing 6 files.
2009-12-29 23:53:09 UTC by arniml
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arniml committed revision 1686 to the Universal JTAG library, server and tools SVN repository, changing 2 files.
2009-12-29 23:35:10 UTC by arniml
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Hello all...
I have solved the problem. The problem was solved by powering the quad OR gate which is being used as a buffer with 5V instead of 3.3V ... not exactly sure why this is but it fixes it ... I can program both the 2.5, 3.3, and digilent board with the signle ft2232D and a quad OR gate ...
thanks for you help ...
regards
Michael.
2009-12-28 02:30:26 UTC by mkabatek
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So i have managed to solve one problem and generate another!
I solved the detect problem by buffering all the signals using OR gates.
Now I have generated an additional problem.
I have two custom boards (same as mentioned above xc3s500e, and xcf04s)... they are almost identical, but the difference between them is that the JTAG voltage for the xcf04s.. one board has 3.3V, the other has...
2009-12-27 19:53:03 UTC by mkabatek
