Hi Everyone!

We have developed vMAGIC in the hope that it will be usefull for a number of VHDL designers who wish to introduce a new level of automation into their work. As we currently only offer the bare library, I can imagine how hard it is to see how usefull vMAGIC is. We will soon add more demos and examples which should easily reveal the power of vMAGIC.
Some of you might say, that the functionality of vMAGIC is "sort of" included in a number of commercially available tools, seeing as a parser is needed nearly everywhere, and source transformators, and generators are used in several products, too. Prominent among the tools who use techniques as in vMAGIC are IP core generators and packagers available from big EDA companies. This is absolutely true, but the problem is that in those cases, the functionality is restricted to the tools and uses in question, and user interaction is limited to the uses forseen by EDA vendors. With vMAGIC, it is possible to program nearly any possible system manipulating VHDL code, and the funtionality needed for that is packaged in one well documented and freely available library.
Therefore, please check out our library now or, if you find anything that is not working as you would expect it to do, please let us know. vMAGIC is under active development and we do appreciate your comments and your help via the forums, and trackers.

Stay tund for the upcoming demos,
yours sincerely,
christopher pohl