I really prefer the VHDL entity instantiation to the old component instantiation because of a defined namespace and less overhead. (See here for an example: http://vhdlguru.blogspot.de/2010/03/entity-instantiation-easy-way-of-port.html)
There seems to be support for these instantiations in VHDL but the name of the library containing the entity is missing. I've patched the code so it will work for me. Perhaps this can be put to the repository if I don't understand something wrong.
I really prefer the VHDL entity instantiation to the old component instantiation because of a defined namespace and less overhead. (See here for an example: http://vhdlguru.blogspot.de/2010/03/entity-instantiation-easy-way-of-port.html)
There seems to be support for these instantiations in VHDL but the name of the library containing the entity is missing. I've patched the code so it will work for me. Perhaps this can be put to the repository if I don't understand something wrong.