This patch adds support for AES in RISC little endian configuration.
Currently configure falls back to CISC when set to little endian. Circumventing this exposes missing parts in the AES implementation, which become apparent during the self test. With this patch the self test does succeed.
In addition to this patch the configure script should be adapted to allow RISC / LE
AES RISC little endian support
In addition to this there's a suspicious line in aes_icm.c.
@@ -310,1 +310,2 @@
- c->counter.v32[3] = htonl(++temp)
+ ++temp;
+ c->counter.v32[3] = htonl(temp);
This comes up when htonl is implemented as a macro and expands in little endian mode.