#2 floating nets generated

open-later
nobody
None
5
2011-11-09
2011-11-09
Anonymous
No

If you use the syntax

wire x = 1;

x will synthesize as a floating net. If instead you use

assign x = 1;

then it works. It would be nice if either syntax was accepted (and worked)

Discussion


  • Anonymous
    2011-11-09

    compressed tar file of good/bad verilog

     
    Attachments
  • sim-sim
    sim-sim
    2011-11-09

    • status: open --> open-later
     
  • sim-sim
    sim-sim
    2011-11-09

    Yes initial value assignments are ignored at this moment.